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    Methods of forming an array of gated devices
    1.
    发明授权
    Methods of forming an array of gated devices 有权
    形成门阵列阵列的方法

    公开(公告)号：US09209187B1

    公开(公告)日：2015-12-08

    申请号：US14461689

    申请日：2014-08-18

    Applicant: Micron Technology, Inc.

    Inventor： Marcello Mariani ,  Alessandro Grossi ,  Federica Zanderigo

    IPC: H01L29/74 ,  H01L27/105 ,  H01L21/8222 ,  H01L27/102 ,  H01L21/768 ,  H01L21/8234 ,  H01L29/66 ,  H01L21/762 ,  H01L21/306 ,  G03F7/20 ,  H01L29/423

    CPC classification number: H01L29/4236 ,  H01L21/8222 ,  H01L21/8229 ,  H01L21/823487 ,  H01L27/1027 ,  H01L27/1052 ,  H01L29/66363 ,  H01L29/66666 ,  H01L29/749 ,  H01L29/7827

    Abstract: A method of forming an array of gated devices includes forming a plurality of semiconductor material-comprising blocks individually projecting elevationally from a substrate and spaced from one another along rows and columns. A gate line is formed laterally proximate each of two opposing sidewalls of the blocks along individual rows of the blocks. After forming the gate lines, semiconductor material of the blocks is removed laterally between the gate lines to form pairs of pillars from the individual blocks that individually have one of the gate lines laterally proximate one of two laterally outermost sidewalls of the pair and another of the gate lines laterally proximate the other of the two laterally outermost sidewalls of the pair. Other methods are disclosed.

    Abstract translation: 一种形成门控器件阵列的方法包括形成多个半导体材料块，它们分别从衬底突出地突出并沿着行和列彼此间隔开。 栅极线沿块的各行的横向靠近块的两个相对的侧壁中的每一个形成。 在形成栅极线之后，块的半导体材料在栅极线之间被横向移除，以形成来自各个块的成对的柱，所述块独立地具有横向靠近该对的两个横向最外侧的侧壁之一的栅极线之一， 栅极线横向靠近该对的两个横向最外侧的另一侧。 公开了其他方法。

    SHALLOW TRENCH ISOLATION FOR A MEMORY
    2.
    发明申请
    SHALLOW TRENCH ISOLATION FOR A MEMORY 有权
    用于记忆的浅层分离

    公开(公告)号：US20140027834A1

    公开(公告)日：2014-01-30

    申请号：US14043704

    申请日：2013-10-01

    Applicant: Micron Technology, Inc

    Inventor： Alessandro Grossi ,  Marcello Mariani ,  Paolo Cappelletti

    IPC: H01L29/788

    CPC classification number: H01L29/788 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/7881

    Abstract: In some embodiments, a gate structure with a spacer on its side may be used as a mask o form self-aligned trenches in microelectronic memory, such as a flash memory. A first portion of the gate structure may be used to form the mask, together with sidewall spacers, in some embodiments. Then, after forming the shallow trench isolations, a second portion of the gate structure may be added to form a mushroom shaped gate structure.

    Abstract translation: 在一些实施例中，具有其侧面上的间隔物的栅极结构可以用作微电子存储器（例如闪存）中的自对准沟槽的掩模。 在一些实施例中，门结构的第一部分可以与侧壁间隔件一起用于形成掩模。 然后，在形成浅沟槽隔离物之后，可以添加栅极结构的第二部分以形成蘑菇形门结构。

    Methods of forming an array of gated devices
    3.
    发明授权
    Methods of forming an array of gated devices 有权
    形成门阵列阵列的方法

    公开(公告)号：US09224738B1

    公开(公告)日：2015-12-29

    申请号：US14461730

    申请日：2014-08-18

    Applicant: Micron Technology, Inc.

    Inventor： Federica Zanderigo ,  Marcello Mariani ,  Alessandro Grossi

    IPC: H01L21/8242 ,  H01L27/105 ,  H01L21/8234 ,  H01L21/768 ,  H01L27/102 ,  H01L21/8222 ,  H01L21/311 ,  H01L21/3213 ,  H01L29/423 ,  H01L21/762

    CPC classification number: H01L29/4236 ,  H01L21/76224 ,  H01L21/823437 ,  H01L21/823475 ,  H01L21/823487 ,  H01L27/1022 ,  H01L27/1027 ,  H01L29/42364

    Abstract: A method of forming an array of gated devices includes forming trenches between walls that longitudinally extend in rows and project elevationally from a substrate. The walls comprise semiconductor material. Gate dielectric is formed within the trenches laterally over side surfaces of the walls and conductive gate material is formed within the trenches laterally over side surfaces of the gate dielectric. Side surfaces of an elevationally inner portion of the gate material within the trenches are laterally covered with masking material and side surfaces of an elevationally inner portion of the gate material within the trenches are laterally uncovered by the masking material. The elevationally outer portion of the gate material that is laterally uncovered by the masking material is removed while the side surfaces of the elevationally inner portion of the gate material are laterally covered by the masking material to form gate lines within the trenches laterally over elevationally inner portions of the walls.

    Abstract translation: 形成浇口装置阵列的方法包括在壁之间形成沟槽，所述沟槽纵向延伸成行并且从衬底高度突出。 壁包括半导体材料。 栅极电介质在沟槽的横向上形成在壁的侧表面上，并且导电栅极材料在栅极电介质的侧表面的横向上形成在沟槽内。 沟槽内栅极材料的正面内部的侧表面被掩蔽材料侧向覆盖，沟槽内栅极材料的正面内部的侧表面被掩蔽材料横向覆盖。 栅极材料横向未被掩模材料覆盖的正面外部部分被去除，同时栅极材料的正面内部的侧表面被掩蔽材料横向覆盖，以在沟槽内部横向地在顶部内部部分上形成栅极线 的墙壁。

    Shallow trench isolation for a memory
    4.
    发明授权
    Shallow trench isolation for a memory 有权
    浅沟槽隔离用于记忆

    公开(公告)号：US08963220B2

    公开(公告)日：2015-02-24

    申请号：US14043704

    申请日：2013-10-01

    Applicant: Micron Technology, Inc

    Inventor： Alessandro Grossi ,  Marcello Mariani ,  Paolo Cappelletti

    IPC: H01L29/76 ,  H01L29/788 ,  H01L27/115 ,  H01L29/423

    CPC classification number: H01L29/788 ,  H01L27/11521 ,  H01L29/42324 ,  H01L29/7881

    Abstract: In some embodiments, a gate structure with a spacer on its side may be used as a mask o form self-aligned trenches in microelectronic memory, such as a flash memory. A first portion of the gate structure may be used to form the mask, together with sidewall spacers, in some embodiments. Then, after forming the shallow trench isolations, a second portion of the gate structure may be added to form a mushroom shaped gate structure.

    Abstract translation: 在一些实施例中，具有其侧面上的间隔物的栅极结构可以用作微电子存储器（例如闪存）中的自对准沟槽的掩模。 在一些实施例中，门结构的第一部分可以与侧壁间隔件一起用于形成掩模。 然后，在形成浅沟槽隔离物之后，可以添加栅极结构的第二部分以形成蘑菇形门结构。

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