公开(公告)号：US20250085859A1

公开(公告)日：2025-03-13

申请号：US18955554

申请日：2024-11-21

Applicant: Micron Technology, Inc.

Inventor： Emanuele Confalonieri ,  Antonino Caprí ,  Nicola Del Gatto ,  Federica Cresci ,  Massimiliano Turconi

IPC: G06F3/06

Abstract: An apparatus can include a plurality of memory devices and a memory controller coupled to the plurality of memory devices via a plurality of memory channels. The plurality of memory channels can be each organized as a plurality of channel groups that can be operated as independent RAS channels (e.g., channels for independent RAS accesses). Data received at the memory controller via different memory channels of one RAS channel can be aligned at various circuits and/or components of the memory controller.

公开(公告)号：US12050780B2

公开(公告)日：2024-07-30

申请号：US17929963

申请日：2022-09-06

Applicant: Micron Technology, Inc.

Inventor： Federica Cresci ,  Massimiliano Patriarca

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/0653 ,  G06F3/0679

Abstract: Methods, systems, and devices for adaptive temperature protection for a memory controller are described. In some cases, a memory system may include a set of temperature sensors distributed across the memory system. The set of temperature sensors may be used to monitor or model the temperature of one or more sections of the memory system. Upon determining that the temperature of a section exceeds a threshold, the memory system may employ one or more mitigation techniques to reduce the temperature or the rate of change of the temperature of the section. For example, the memory system may reduce a clock frequency corresponding to the section, while maintaining separate clock frequencies for other sections of the memory system. Additionally or alternatively, the memory system may transfer data or other information from the section to a separate section.

公开(公告)号：US20240184457A1

公开(公告)日：2024-06-06

申请号：US18527990

申请日：2023-12-04

Applicant: Micron Technology, Inc.

Inventor： Angelo Alberto Rovelli ,  Federica Cresci

IPC: G06F3/06

CPC classification number: G06F3/0622 ,  G06F3/0655 ,  G06F3/0679

Abstract: An access controller can be provided to regulate and secure access to an intermediate memory to which data stored in a one-time-programmable (OTP) memory can be copied. To secure the access of the intermediate memory, the access controller can regulate a frequency at which the intermediate memory can be accessed and cryptographically manage (e.g., encrypt and/or decrypt) data being read from and/or written to the intermediate memory.

公开(公告)号：US20240078021A1

公开(公告)日：2024-03-07

申请号：US17929963

申请日：2022-09-06

Applicant: Micron Technology, Inc.

Inventor： Federica Cresci ,  Massimiliano Patriarca

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/0653 ,  G06F3/0679

Abstract: Methods, systems, and devices for adaptive temperature protection for a memory controller are described. In some cases, a memory system may include a set of temperature sensors distributed across the memory system. The set of temperature sensors may be used to monitor or model the temperature of one or more sections of the memory system. Upon determining that the temperature of a section exceeds a threshold, the memory system may employ one or more mitigation techniques to reduce the temperature or the rate of change of the temperature of the section. For example, the memory system may reduce a clock frequency corresponding to the section, while maintaining separate clock frequencies for other sections of the memory system. Additionally or alternatively, the memory system may transfer data or other information from the section to a separate section.

公开(公告)号：US12124729B2

公开(公告)日：2024-10-22

申请号：US17687018

申请日：2022-03-04

Applicant: Micron Technology, Inc.

Inventor： Nicola Del Gatto ,  Federica Cresci ,  Emanuele Confalonieri

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/061 ,  G06F3/0673

Abstract: Systems, apparatuses, and methods related to a controller for managing metrics and telemetry are described. A controller includes a front end portion, a central controller portion, a back end portion, and a management unit. The central controller portion can include a cache to store data associated with the performance of the memory operations, metric logic configured to collect metrics related to performance of the memory operations, load telemetry logic configured to collect load telemetry associated with performance of the memory operations within a threshold time, and a storage area to store the collected metrics and the collected load telemetry. The management unit memory of the controller can store metrics and load telemetry associatAND ed with monitoring the characteristics of the memory controller, and based on the stored metrics and load telemetry, alter at least one characteristic of the computing system.

公开(公告)号：US20230205462A1

公开(公告)日：2023-06-29

申请号：US18089010

申请日：2022-12-27

Applicant: Micron Technology, Inc.

Inventor： Federica Cresci ,  Nicola Del Gatto ,  Massimiliano Turconi ,  Massimiliano Patriarca

IPC: G06F3/06 ,  G06F12/02

CPC classification number: G06F3/0659 ,  G06F3/0656 ,  G06F12/0246 ,  G06F3/0683 ,  G06F3/0613

Abstract: Methods, systems, and devices for event management for memory devices are described. A memory system may include a frontend (FE) queue and a backend (BE). Each queue may include an interface that can be operated in an interrupt mode or a polling mode based on certain metrics. For example, the interface associated with the FE queue may be operated in a polling mode or an interrupt mode based on whether a quantity of commands being executed on one or more memory devices of the memory system satisfies a threshold value. Additionally or alternatively, the interface associated with the BE queue may be operated in a polling mode or an interrupt mode based on whether a quantity of active logical block addresses (LBAs) associated with one or more operations being executed on one or more memory devices of the memory system satisfies a threshold value.

公开(公告)号：US20220207193A1

公开(公告)日：2022-06-30

申请号：US17562916

申请日：2021-12-27

Applicant: Micron Technology, Inc.

Inventor： Danilo Caraccio ,  Federica Cresci ,  Alessandro Orlando ,  Paolo Amato ,  Angelo Alberto Rovelli ,  Craig A. Jones ,  Niccolò Izzo

IPC: G06F21/79 ,  G06F21/60 ,  G06F21/55 ,  G11C11/22

Abstract: Systems, apparatuses, and methods related to security management for a ferroelectric memory device are described. An example method can include receiving, at a memory controller and from a host, a command and firmware data. The memory controller can manage a non-volatile memory device, such as a ferroelectric memory device, and the host and the memory controller can communicate using a compute express link (CXL) protocol. The command can be executed to update firmware stored on the non-volatile memory device. The method can further include accessing a first public key from the non-volatile memory device. The method can further include validating the first public key with a second public key within the firmware data. The method can further include validating the firmware data. The method can further include verifying a security version of the firmware data. The method can further include updating the non-volatile memory device with the firmware data.

公开(公告)号：US20220057958A1

公开(公告)日：2022-02-24

申请号：US16950596

申请日：2020-11-17

Applicant: Micron Technology, Inc.

Inventor： Massimiliano Patriarca ,  Nicola Del Gatto ,  Massimiliano Turconi ,  Federica Cresci

IPC: G06F3/06

Abstract: Methods, systems, and devices for adaptive buffer partitioning are described. A memory system may include a buffer for storing data (e.g., associated with a read command or a write command received from a host system). For example, the buffer may buffer data associated with a write command prior to storing the data at a memory device of the memory system. In another example, the buffer may buffer data associated with a read command prior to transmitting the data to the host system. In some cases, the buffer may include a first portion configured to store data associated with one or more read commands, a second portion configured to store data associated with one or more write commands, and a third portion configured to store data associated with one or more read commands or one or more write commands.

公开(公告)号：US12197631B2

公开(公告)日：2025-01-14

申请号：US17562916

申请日：2021-12-27

Applicant: Micron Technology, Inc.

Inventor： Danilo Caraccio ,  Federica Cresci ,  Alessandro Orlando ,  Paolo Amato ,  Angelo Alberto Rovelli ,  Craig A. Jones ,  Niccolò Izzo

IPC: G06F21/79 ,  G06F21/10 ,  G06F21/55 ,  G06F21/60 ,  G11C11/22

Abstract: Systems, apparatuses, and methods related to security management for a ferroelectric memory device are described. An example method can include receiving, at a memory controller and from a host, a command and firmware data. The memory controller can manage a non-volatile memory device, such as a ferroelectric memory device, and the host and the memory controller can communicate using a compute express link (CXL) protocol. The command can be executed to update firmware stored on the non-volatile memory device. The method can further include accessing a first public key from the non-volatile memory device. The method can further include validating the first public key with a second public key within the firmware data. The method can further include validating the firmware data. The method can further include verifying a security version of the firmware data. The method can further include updating the non-volatile memory device with the firmware data.

公开(公告)号：US12164773B2

公开(公告)日：2024-12-10

申请号：US17968049

申请日：2022-10-18

Applicant: Micron Technology, Inc.

Inventor： Emanuele Confalonieri ,  Antonino Capri ,  Nicola Del Gatto ,  Federica Cresci ,  Massimiliano Turconi

IPC: G06F3/06

Abstract: An apparatus can include a plurality of memory devices and a memory controller coupled to the plurality of memory devices via a plurality of memory channels. The plurality of memory channels can be each organized as a plurality of channel groups that can be operated as independent RAS channels (e.g., channels for independent RAS accesses). Data received at the memory controller via different memory channels of one RAS channel can be aligned at various circuits and/or components of the memory controller.