公开(公告)号：US20190340125A1

公开(公告)日：2019-11-07

申请号：US15971653

申请日：2018-05-04

Applicant: Micron Technology, Inc.

Inventor： Antonino Mondello ,  Francesco Tomaiuolo ,  Salvatore Giove ,  Pierluca Guarino ,  Fabio Indelicato ,  Marco Ruta ,  Maria Luisa Gambina ,  Giovanni Nunzio Maria Avenia ,  Carmela Maria Calafato

IPC: G06F12/0811 ,  G06F11/10 ,  G11C29/52

Abstract: Apparatuses, systems, and methods to perform continuous read operations are described. A system configured to perform such continuous read operations enables improved access to and processing of data for performance of associated functions. For instance, one apparatus described herein includes a memory device having an array that includes a plurality of pages of memory cells. The memory device includes a page buffer coupled to the array and a continuous read buffer. The continuous read buffer includes a first cache to receive a first segment of data values and a second cache to receive a second segment of the data values from the page buffer. The memory device is configured to perform a continuous read operation on the first and second segments of data from the first cache and the second cache of the continuous read buffer.

公开(公告)号：US11657877B2

公开(公告)日：2023-05-23

申请号：US17366786

申请日：2021-07-02

Applicant: Micron Technology, Inc.

Inventor： Antonino Mondello ,  Francesco Tomaiuolo ,  Carmelo Condemi ,  Tommaso Zerilli

IPC: G06F11/08 ,  G11C16/10 ,  G11C16/16 ,  H03K21/40 ,  G11C16/34

CPC classification number: G11C16/105 ,  G06F11/08 ,  G11C16/16 ,  G11C16/3436 ,  H03K21/403 ,  G06F2212/202

Abstract: An apparatus, such as a memory (e.g., a NAND memory), can have a controller, a volatile counter coupled to the controller, and a non-volatile memory array coupled to the controller. The controller can be configured to write information, other than a count of the counter, in the array each time the count of the counter has been incremented by a particular number of increments. Counts can be monotonic, non-volatile, and power-loss tolerant.

公开(公告)号：US20200233967A1

公开(公告)日：2020-07-23

申请号：US16255142

申请日：2019-01-23

Applicant: Micron Technology, Inc.

Inventor： Antonino Mondello ,  Carmelo Condemi ,  Francesco Tomaiuolo ,  Tommaso Zerilli

IPC: G06F21/60 ,  H04L9/32 ,  G06F11/10 ,  G11C29/52 ,  H03M13/29

Abstract: An apparatus, such as a memory system (e.g., a NAND memory system), can have a controller with a first error correction code component and a memory device (e.g., a NAND memory device) coupled to the controller. The memory device can have an array of memory cells, a second error correction code component coupled to the array and configured to correct data from the array, and a cryptographic component coupled to receive the corrected data from the second error correction code component.

公开(公告)号：US20210335425A1

公开(公告)日：2021-10-28

申请号：US17366786

申请日：2021-07-02

Applicant: Micron Technology, Inc.

Inventor： Antonino Mondello ,  Francesco Tomaiuolo ,  Carmelo Condemi ,  Tommaso Zerilli

IPC: G11C16/10 ,  G11C16/16 ,  G06F11/08 ,  H03K21/40 ,  G11C16/34

Abstract: An apparatus, such as a memory (e.g., a NAND memory), can have a controller, a volatile counter coupled to the controller, and a non-volatile memory array coupled to the controller. The controller can be configured to write information, other than a count of the counter, in the array each time the count of the counter has been incremented by a particular number of increments. Counts can be monotonic, non-volatile, and power-loss tolerant.

公开(公告)号：US20230086754A1

公开(公告)日：2023-03-23

申请号：US17994680

申请日：2022-11-28

Applicant: Micron Technology, Inc.

Inventor： Antonino Mondello ,  Carmelo Condemi ,  Francesco Tomaiuolo ,  Tommaso Zerilli

IPC: G06F21/60 ,  H04L9/32 ,  H03M13/29 ,  G06F11/10 ,  G11C29/52 ,  G06F21/64 ,  G06F21/79

Abstract: An apparatus, such as a memory system (e.g., a NAND memory system), can have a controller with a first error correction code component and a memory device (e.g., a NAND memory device) coupled to the controller. The memory device can have an array of memory cells, a second error correction code component coupled to the array and configured to correct data from the array, and a cryptographic component coupled to receive the corrected data from the second error correction code component.

公开(公告)号：US20230039804A1

公开(公告)日：2023-02-09

申请号：US17895693

申请日：2022-08-25

Applicant: Micron Technology, Inc.

Inventor： Antonino Mondello ,  Tommasso Zerilli ,  Carmelo Condemi ,  Francesco Tomaiuolo

IPC: H04L9/32 ,  G11C16/26 ,  G11C16/04 ,  G11C16/14 ,  G06F21/72 ,  G11C16/10

Abstract: Various examples described herein are directed to systems and methods for generating data values using a NAND flash array. A memory controller may read a number of memory cells at the NAND flash array using an initial read level to generate a first raw string. The memory controller may determine that a difference between a number of bits from the first raw string having a value of logical zero and a number of bits from the first raw string having a value of logical one is greater than a threshold value and read the number of memory cells using a second read level to generate a second raw string. The memory controller may determine that a difference between a number of bits from the second raw string having a value of logical zero and a number of bits from the second raw string having a value of logical one is not greater than a threshold value and applying a cryptographic function using the second raw string to generate a first PUF value.

公开(公告)号：US11469909B2

公开(公告)日：2022-10-11

申请号：US16236005

申请日：2018-12-28

Applicant: Micron Technology, Inc.

Inventor： Antonino Mondello ,  Tommaso Zerilli ,  Carmelo Condemi ,  Francesco Tomaiuolo

IPC: G11C16/14 ,  H04L9/32 ,  G11C16/26 ,  G11C16/04 ,  G06F21/72 ,  G11C16/10 ,  G11C11/56

Abstract: Various examples described herein are directed to systems and methods for generating data values using a NAND flash array. A memory controller may read a number of memory cells at the NAND flash array using an initial read level to generate a first raw string. The memory controller may determine that a difference between a number of bits from the first raw string having a value of logical zero and a number of bits from the first raw string having a value of logical one is greater than a threshold value and read the number of memory cells using a second read level to generate a second raw string. The memory controller may determine that a difference between a number of bits from the second raw string having a value of logical zero and a number of bits from the second raw string having a value of logical one is not greater than a threshold value and applying a cryptographic function using the second raw string to generate a first PUF value.

公开(公告)号：US11056192B2

公开(公告)日：2021-07-06

申请号：US16229609

申请日：2018-12-21

Applicant: Micron Technology, Inc.

Inventor： Antonino Mondello ,  Francesco Tomaiuolo ,  Carmelo Condemi ,  Tommaso Zerilli

IPC: G11C16/10 ,  G11C16/16 ,  G06F11/08 ,  H03K21/40 ,  G11C16/34

Abstract: An apparatus, such as a memory (e.g., a NAND memory), can have a controller, a volatile counter coupled to the controller, and a non-volatile memory array coupled to the controller. The controller can be configured to write information, other than a count of the counter, in the array each time the count of the counter has been incremented by a particular number of increments. Counts can be monotonic, non-volatile, and power-loss tolerant.

公开(公告)号：US20200213138A1

公开(公告)日：2020-07-02

申请号：US16236005

申请日：2018-12-28

Applicant: Micron Technology, Inc.

Inventor： Antonino Mondello ,  Tommaso Zerilli ,  Carmelo Condemi ,  Francesco Tomaiuolo

IPC: H04L9/32 ,  G11C16/26 ,  G11C16/04 ,  G11C16/14 ,  G11C16/10 ,  G06F21/72

Abstract: Various examples described herein are directed to systems and methods for generating data values using a NAND flash array. A memory controller may read a number of memory cells at the NAND flash array using an initial read level to generate a first raw string. The memory controller may determine that a difference between a number of bits from the first raw string having a value of logical zero and a number of bits from the first raw string having a value of logical one is greater than a threshold value and read the number of memory cells using a second read level to generate a second raw string. The memory controller may determine that a difference between a number of bits from the second raw string having a value of logical zero and a number of bits from the second raw string having a value of logical one is not greater than a threshold value and applying a cryptographic function using the second raw string to generate a first PUF value.

公开(公告)号：US11868488B2

公开(公告)日：2024-01-09

申请号：US17994680

申请日：2022-11-28

Applicant: Micron Technology, Inc.

Inventor： Antonino Mondello ,  Carmelo Condemi ,  Francesco Tomaiuolo ,  Tommaso Zerilli

IPC: G06F11/30 ,  G06F12/14 ,  G06F21/60 ,  H04L9/32 ,  H03M13/29 ,  G06F11/10 ,  G11C29/52 ,  G06F21/64 ,  G06F21/79

CPC classification number: G06F21/602 ,  G06F11/1068 ,  G06F21/64 ,  G06F21/79 ,  G11C29/52 ,  H03M13/2906 ,  H04L9/3242 ,  H04L9/3278

Abstract: An apparatus, such as a memory system (e.g., a NAND memory system), can have a controller with a first error correction code component and a memory device (e.g., a NAND memory device) coupled to the controller. The memory device can have an array of memory cells, a second error correction code component coupled to the array and configured to correct data from the array, and a cryptographic component coupled to receive the corrected data from the second error correction code component.