公开(公告)号：US20250159945A1

公开(公告)日：2025-05-15

申请号：US19020106

申请日：2025-01-14

Applicant: Micron Technology, Inc.

Inventor： Manzar Siddik ,  Terry H. Kim

IPC: H10D30/69 ,  G11C16/04 ,  H10B43/20 ,  H10B43/30

Abstract: Some embodiments include a memory cell having charge-trapping-material between a semiconductor channel material and a gating region. The charge-trapping-material includes silicon, nitrogen and trap-enhancing-additive. The trap-enhancing-additive includes one or more of carbon, phosphorus, boron and metal. Some embodiments include an integrated assembly having a stack of alternating first and second levels. The first levels include conductive structures and the second levels are insulative. Channel-material-pillars extend through the stack. Charge-trapping-regions are along the channel-material-pillars and are between the channel-material-pillars and the conductive structures. The charge-trapping-regions include a charge-trapping-material which contains silicon, nitrogen and trap-enhancing-additive. The trap-enhancing-additive includes one or more of carbon, phosphorus, boron and metal.

公开(公告)号：US12261210B2

公开(公告)日：2025-03-25

申请号：US17176444

申请日：2021-02-16

Applicant: Micron Technology, Inc.

Inventor： Manzar Siddik ,  Terry H. Kim ,  Kyubong Jung

IPC: H01L29/51 ,  H01L21/28 ,  H01L29/423 ,  H10B43/27

Abstract: A method of forming an electronic device comprising forming an initial dielectric material comprising silicon-hydrogen bonds. A deuterium source gas and an oxygen source gas are reacted to produce deuterium species, and the initial dielectric material is exposed to the deuterium species. Deuterium of the deuterium species is incorporated into the initial dielectric material to form a deuterium-containing dielectric material. Additional methods are also disclosed, as are electronic devices and systems comprising the deuterium-containing dielectric material.

公开(公告)号：US20220020685A1

公开(公告)日：2022-01-20

申请号：US17489262

申请日：2021-09-29

Applicant: Micron Technology, Inc.

Inventor： Hongqi Li ,  Kaushik Varma Sagi ,  Manzar Siddik

IPC: H01L23/522 ,  H01L21/768

Abstract: Methods and apparatuses for slit oxide and via formation techniques are described, for example, for fabricating three dimensional memory devices that may include multiple decks of memory cells that each include memory cell stacks and associated access lines. The techniques may create an interconnect region without removing a portion of the memory cell stacks. The interconnect region may include one or more conductive vias extending through the decks of memory cells to couple the access lines with logic circuitry that may be located underneath the decks of memory cells. Further, the techniques may divide an array of memory cells into multiple subarrays of memory cells by forming trenches, which may sever the access lines. In some cases, each subarray of memory cells may be electrically isolated from other subarrays of memory cells. The techniques may reduce a total number of fabrication process steps.

公开(公告)号：US20210175247A1

公开(公告)日：2021-06-10

申请号：US16705388

申请日：2019-12-06

Applicant: Micron Technology, Inc.

Inventor： Manzar Siddik ,  Chris M. Carlson ,  Terry H. Kim ,  Kunal Shrotri ,  Srinath Venkatesan

IPC: H01L27/11582 ,  H01L27/11556 ,  H01L21/3115 ,  H01L21/3215

Abstract: A memory array comprising strings of memory cells comprises a vertical stack comprising alternating insulative tiers and conductive tiers. The strings of memory cells in the stack comprise channel-material strings and storage-material strings extending through the insulative tiers and the conductive tiers. At least some of the storage material of the storage-material strings in individual of the insulative tiers are intrinsically less charge-transmissive than is the storage material in the storage-material strings in individual of the conductive tiers. Other aspects, including method, are disclosed.

公开(公告)号：US20180331113A1

公开(公告)日：2018-11-15

申请号：US15590863

申请日：2017-05-09

Applicant: Micron Technology, Inc.

Inventor： Albert Liao ,  Wayne I. Kinney ,  Yi Fang Lee ,  Manzar Siddik

IPC: H01L27/11507 ,  H01L27/11509 ,  H01L49/02 ,  G11C11/22

CPC classification number: H01L27/11507 ,  G11C11/221 ,  G11C11/2297 ,  H01L27/11509 ,  H01L28/55

Abstract: A semiconductor structure includes an electrode, a ferroelectric material adjacent the electrode, the ferroelectric material comprising an oxide of at least one of hafnium and zirconium, the ferroelectric material doped with bismuth, and another electrode adjacent the ferroelectric material on an opposite side thereof from the first electrode. Related semiconductor structures, memory cells, semiconductor devices, electronic systems, and related methods are disclosed.

公开(公告)号：US20170331032A1

公开(公告)日：2017-11-16

申请号：US15588994

申请日：2017-05-08

Applicant: Micron Technology, Inc.

Inventor： Wei Chen ,  Witold Kula ,  Manzar Siddik ,  Suresh Ramarajan ,  Jonathan D. Harms

IPC: H01L43/02 ,  H01L43/10 ,  H01L27/22

CPC classification number: H01L43/02 ,  G11C11/161 ,  H01L27/224 ,  H01L43/08 ,  H01L43/10

Abstract: A magnetic tunnel junction comprises a conductive first magnetic electrode comprising magnetic recording material, a conductive second magnetic electrode spaced from the first electrode and comprising magnetic reference material, and a non-magnetic tunnel insulator material between the first and second electrodes. The magnetic reference material of the second electrode comprises a synthetic antiferromagnetic construction comprising two spaced magnetic regions one of which is closer to the tunnel insulator material than is the other. The one magnetic region comprises a polarizer region comprising CoxFeyBz where “x” is from 0 to 90, “y” is from 10 to 90, and “z” is from 10 to 50. The CoxFeyBz is directly against the tunnel insulator. A non-magnetic region comprising an Os-containing material is between the two spaced magnetic regions. The other magnetic region comprises a magnetic Co-containing material. Other embodiments are disclosed.

公开(公告)号：US09553259B2

公开(公告)日：2017-01-24

申请号：US15000620

申请日：2016-01-19

Applicant: Micron Technology, Inc.

Inventor： Manzar Siddik

IPC: G11B5/127 ,  H01L43/10 ,  H01L43/02 ,  H01L43/08

CPC classification number: H01L43/10 ,  G11B5/127 ,  G11C11/161 ,  H01L43/02 ,  H01L43/08

Abstract: A magnetic tunnel junction comprises a conductive first magnetic electrode comprising magnetic recording material. A conductive second magnetic electrode is spaced from the first electrode and comprises magnetic reference material. A non-magnetic tunnel insulator material is between the first and second electrodes. The magnetic recording material of the first electrode comprises a first crystalline magnetic region, in one embodiment comprising Co and Fe. In one embodiment, the first electrode comprises a second amorphous region comprising amorphous XN, where X is one or more of W, Mo, Cr, V, Nb, Ta, Al, and Ti. In one embodiment, the first electrode comprises a second region comprising Co, Fe, and N.

Abstract translation: 磁性隧道结包括包含磁记录材料的导电第一磁性电极。 导电的第二磁电极与第一电极间隔开并且包括磁性参考材料。 非磁性隧道绝缘体材料位于第一和第二电极之间。 第一电极的磁记录材料包括第一结晶磁性区域，在一个实施方案中包括Co和Fe。 在一个实施例中，第一电极包括包含非晶XN的第二非晶区域，其中X是W，Mo，Cr，V，Nb，Ta，Al和Ti中的一种或多种。 在一个实施例中，第一电极包括包含Co，Fe和N的第二区域。

公开(公告)号：US20160308123A1

公开(公告)日：2016-10-20

申请号：US14687317

申请日：2015-04-15

Applicant: Micron Technology, Inc.

Inventor： Manzar Siddik ,  Witold Kula ,  Gurtej S. Sandhu

IPC: H01L43/12 ,  H01L43/10 ,  H01L43/08

CPC classification number: H01L43/12 ,  G11C11/161 ,  H01L43/08 ,  H01L43/10

Abstract: A method of forming a magnetic electrode of a magnetic tunnel junction comprises forming non-magnetic MgO-comprising material over conductive material of the magnetic electrode being formed. An amorphous metal is formed over the MgO-comprising material. Amorphous magnetic electrode material comprising Co and Fe is formed over the amorphous metal. The amorphous magnetic electrode material is devoid of B. Non-magnetic tunnel insulator material comprising MgO is formed directly against the amorphous magnetic electrode material. The tunnel insulator material is devoid of B. After forming the tunnel insulator material, the amorphous Co and Fe-comprising magnetic electrode material is annealed at a temperature of at least about 250° C. to form crystalline Co and Fe-comprising magnetic electrode material from an MgO-comprising surface of the tunnel insulator material. The crystalline Co and Fe-comprising magnetic electrode material is devoid of B. Other method and non-method embodiments are disclosed.

Abstract translation: 形成磁性隧道结的磁极的方法包括在形成的磁极的导电材料上形成非磁性的含MgO材料。 在包含MgO的材料上形成无定形金属。 包含Co和Fe的非晶磁性电极材料形成在无定形金属上。 无定形磁极材料不含B.直接与非晶磁性电极材料形成包含MgO的非磁性隧道绝缘体材料。 隧道绝缘体材料没有B.在形成隧道绝缘体材料之后，在至少约250℃的温度下对包含无定形Co和Fe的磁性电极材料进行退火以形成含Co和Fe的结晶的电极材料 从隧道绝缘体材料的包含MgO的表面。 含有Co和Fe的结晶的电极材料不含B。公开了其它方法和非方法的实施方案。

公开(公告)号：US20160211446A1

公开(公告)日：2016-07-21

申请号：US15084688

申请日：2016-03-30

Applicant: Micron Technology, Inc.

Inventor： Manzar Siddik ,  Witold Kula

IPC: H01L43/12 ,  H01L43/08 ,  H01L43/10 ,  H01L43/02

CPC classification number: H01L43/12 ,  H01L43/02 ,  H01L43/08 ,  H01L43/10

Abstract: Spin transfer torque memory cells and methods of forming the same are described herein. As an example, spin transfer torque memory cells may include an amorphous material, a storage material formed on the amorphous material, wherein the storage material is substantially boron free, an interfacial perpendicular magnetic anisotropy material formed on the storage material, a reference material formed on the interfacial perpendicular magnetic anisotropy material, wherein the reference material is substantially boron free, a buffer material formed on the reference material and a pinning material formed on the buffer material.

公开(公告)号：US20160211440A1

公开(公告)日：2016-07-21

申请号：US14597903

申请日：2015-01-15

Applicant: Micron Technology, Inc.

Inventor： Manzar Siddik ,  Witold Kula ,  Suresh Ramarajan

IPC: H01L43/08 ,  G11C11/16 ,  H01L43/12 ,  H01L43/02 ,  H01L43/10

CPC classification number: H01L43/08 ,  G11C11/161 ,  H01L43/12

Abstract: A semiconductor device comprises an array of magnetic cell structures each comprising a magnetic tunnel junction over an electrode on a substrate. Each of the magnetic tunnel junctions includes a magnetic material over the substrate, a first tunnel barrier material over the magnetic material, a second tunnel barrier material over the annealed first tunnel barrier material, and another magnetic material over the second tunnel barrier material. Each magnetic tunnel junction is configured to exhibit a tunnel magnetoresistance greater than or equal to about 180% at a resistance area product of less than about 8 ohm μm2. The semiconductor device also includes another electrode over the another magnetic material. Semiconductor devices including the magnetic tunnel junctions, methods of forming the magnetic tunnel junctions, and methods of forming semiconductor devices including the magnetic tunnel junctions are disclosed.

Abstract translation: 半导体器件包括磁性单元结构的阵列，每个磁性单元结构包括在衬底上的电极上的磁性隧道结。 每个磁性隧道结包括在该基底上的磁性材料，在该磁性材料上方的第一隧道阻挡材料，该退火的第一隧道屏障材料上方的第二隧道阻挡材料，以及该第二隧道屏障材料上的另一种磁性材料。 每个磁性隧道结被配置为在小于约8欧姆·μm2的电阻面积产生大于或等于约180％的隧道磁阻。 半导体器件还包括在另一磁性材料上的另一电极。 公开了包括磁隧道结的半导体器件，形成磁隧道结的方法，以及形成包括磁性隧道结的半导体器件的方法。