公开(公告)号：US20240274526A1

公开(公告)日：2024-08-15

申请号：US18440404

申请日：2024-02-13

Applicant: Micron Technology, Inc.

Inventor： Tsuyoshi Tomoyama ,  Protyush Sahu ,  Hiromitsu Oshima ,  Jeffery B. Hull ,  Satoru Sugiyama ,  Soichi Sugiura

IPC: H01L23/522 ,  H01L23/528 ,  H10B12/00

CPC classification number: H01L23/5226 ,  H01L23/5283 ,  H10B12/03 ,  H10B12/05 ,  H10B12/482 ,  H10B12/485

Abstract: A method used in forming memory circuitry comprises forming transistors of individual memory cells. The transistors individually comprise one source/drain region and another source/drain region. The one and another source/drain regions comprise conductively-doped monocrystalline semiconductive material. A channel region is between the one and the another source/drain regions. A conductive gate is operatively proximate the channel region. Masking material is formed directly above the one and another source/drain regions. The masking material has openings there-through that extend to and are individually directly above individual of the one source/drain regions. Conductively-doped monocrystalline semiconductor material is epitaxially grown from the conductively-doped monocrystalline semiconductive material of the individual one source/drain regions within individual of the openings to form conductive islands that are individually directly above and directly against the individual one source/drain regions in the individual openings. Storage elements of the individual memory cells are formed. The storage elements individually are above and electrically coupled to the individual one source/drain regions through individual of the conductive islands comprising the epitaxially-grown conductively-doped monocrystalline semiconductor material. Other embodiments, including structure, are disclosed.

公开(公告)号：US20240334676A1

公开(公告)日：2024-10-03

申请号：US18427740

申请日：2024-01-30

Applicant: Micron Technology, Inc.

Inventor： Jay S. Brown ,  Protyush Sahu ,  Shuai Jia ,  Jeffery B. Hull ,  Silvia Borsari ,  Li Wei Fang ,  Vivek Y. Yadav ,  Jaidah Mohan

IPC: H10B12/00 ,  H01L21/02 ,  H01L21/768

CPC classification number: H10B12/30 ,  H01L21/02592 ,  H01L21/02598 ,  H01L21/02609 ,  H01L21/76897

Abstract: An apparatus comprises a memory array comprising access lines, digit lines, and memory cells. Each memory cell is coupled to an associated access line and an associated digit line and each memory cell comprises an access device, and a monocrystalline semiconductor material adjacent to the access device. A width of the monocrystalline semiconductor material is within a range of from about 8 nm to about 25 nm. Each memory cell comprises a metal silicide material over the monocrystalline semiconductor material, a metal contact material over the metal silicide material, and a storage node adjacent to the metal contact material. Methods of forming an apparatus and systems are also disclosed.

公开(公告)号：US20240332015A1

公开(公告)日：2024-10-03

申请号：US18427756

申请日：2024-01-30

Applicant: Micron Technology, Inc.

Inventor： Protyush Sahu ,  Mikhail A. Treger ,  Yi Fang Lee ,  Jay S. Brown ,  Shuai Jia ,  Jaidah Mohan ,  Silvia Borsari ,  Richard Beeler ,  Jeffery B. Hull ,  Prashant Raghu

IPC: H01L21/02 ,  H01L21/4763 ,  H10B12/00

CPC classification number: H01L21/02592 ,  H01L21/02598 ,  H01L21/47635 ,  H10B12/02

Abstract: A method of forming an apparatus comprises forming a crystalline semiconductor material comprising one or more of a monocrystalline material and a nanocrystalline material adjacent to active areas of memory cells, forming an amorphous material within portions of the crystalline semiconductor material, forming a metal material comprising one or more of chlorine atoms and nitrogen atoms over the amorphous material, converting a portion of the amorphous material and the metal material to form a metal silicide material adjacent to the crystalline semiconductor material, forming cell contacts over the metal silicide material, and forming a storage node adjacent to the cell contacts. Additional methods and apparatus are also disclosed.