公开(公告)号：US20240321327A1

公开(公告)日：2024-09-26

申请号：US18677609

申请日：2024-05-29

Applicant: Micron Technology, Inc.

Inventor： Byung S. Moon ,  Ramachandra Rao Jogu

IPC: G11C7/10

CPC classification number: G11C7/1039 ,  G11C7/1012 ,  G11C7/1063 ,  G11C7/109

Abstract: The present disclosure includes apparatuses, methods, and systems for pre-decoder circuitry. An embodiment includes a memory array including a plurality of memory cells, decoder circuitry coupled to the memory array, wherein the decoder circuitry comprises a first n-type transistor having a first gate and a second n-type transistor having a second gate, and pre-decoder circuitry configured to provide a bias condition for the first gate and second gate to provide a selection signal to one of the plurality of memory cells, wherein the bias condition comprises: a positive voltage for the first gate and a negative voltage for the second gate for a positive configuration for the memory cells, and zero volts for the first gate and the negative voltage for the second gate for a negative configuration for the memory cells.

公开(公告)号：US20240265965A1

公开(公告)日：2024-08-08

申请号：US18639690

申请日：2024-04-18

Applicant: Micron Technology, Inc.

Inventor： Vijayakrishna J. Vankayala ,  Hari Giduturi ,  Jeffrey E. Koelling ,  Mingdong Cui ,  Ramachandra Rao Jogu

IPC: G11C13/00 ,  H03K19/20

CPC classification number: G11C13/0023 ,  G11C13/0004 ,  G11C2213/15 ,  H03K19/20

Abstract: The present disclosure includes apparatuses, methods, and systems for pre-decoder circuitry. An embodiment includes a memory array including a plurality of memory cells, decoder circuitry coupled to the memory array, wherein the decoder circuitry comprises a p-type transistor having a first gate, a first n-type transistor having a second gate, and a second n-type transistor having a third gate, and pre-decoder circuitry configured to provide a bias condition for the first gate, the second gate, and the third gate to provide a selection signal to one of the plurality of memory cells, wherein the bias condition comprises zero volts for the first gate, the second gate, and the third gate for a positive configuration for the memory cells and a negative voltage for the third gate and zero volts for the first gate and the second gate for a negative configuration for the memory cells.

公开(公告)号：US12002537B2

公开(公告)日：2024-06-04

申请号：US17831290

申请日：2022-06-02

Applicant: Micron Technology, Inc.

Inventor： Byung S. Moon ,  Ramachandra Rao Jogu

IPC: G11C7/10

CPC classification number: G11C7/1039 ,  G11C7/1012 ,  G11C7/1063 ,  G11C7/109

Abstract: The present disclosure includes apparatuses, methods, and systems for pre-decoder circuitry. An embodiment includes a memory array including a plurality of memory cells, decoder circuitry coupled to the memory array, wherein the decoder circuitry comprises a first n-type transistor having a first gate and a second n-type transistor having a second gate, and pre-decoder circuitry configured to provide a bias condition for the first gate and second gate to provide a selection signal to one of the plurality of memory cells, wherein the bias condition comprises: a positive voltage for the first gate and a negative voltage for the second gate for a positive configuration for the memory cells, and zero volts for the first gate and the negative voltage for the second gate for a negative configuration for the memory cells.

公开(公告)号：US20230395104A1

公开(公告)日：2023-12-07

申请号：US17831290

申请日：2022-06-02

Applicant: Micron Technology, Inc.

Inventor： Byung S. Moon ,  Ramachandra Rao Jogu

IPC: G11C7/10

CPC classification number: G11C7/1039 ,  G11C7/1012 ,  G11C7/109 ,  G11C7/1063

Abstract: The present disclosure includes apparatuses, methods, and systems for pre-decoder circuitry. An embodiment includes a memory array including a plurality of memory cells, decoder circuitry coupled to the memory array, wherein the decoder circuitry comprises a first n-type transistor having a first gate and a second n-type transistor having a second gate, and pre-decoder circuitry configured to provide a bias condition for the first gate and second gate to provide a selection signal to one of the plurality of memory cells, wherein the bias condition comprises: a positive voltage for the first gate and a negative voltage for the second gate for a positive configuration for the memory cells, and zero volts for the first gate and the negative voltage for the second gate for a negative configuration for the memory cells.

公开(公告)号：US11967373B2

公开(公告)日：2024-04-23

申请号：US17831311

申请日：2022-06-02

Applicant: Micron Technology, Inc.

Inventor： Vijayakrishna J. Vankayala ,  Hari Giduturi ,  Jeffrey E. Koelling ,  Mingdong Cui ,  Ramachandra Rao Jogu

IPC: G11C13/00 ,  H03K19/20

CPC classification number: G11C13/0023 ,  G11C13/0004 ,  G11C2213/15 ,  H03K19/20

Abstract: The present disclosure includes apparatuses, methods, and systems for pre-decoder circuitry. An embodiment includes a memory array including a plurality of memory cells, decoder circuitry coupled to the memory array, wherein the decoder circuitry comprises a p-type transistor having a first gate, a first n-type transistor having a second gate, and a second n-type transistor having a third gate, and pre-decoder circuitry configured to provide a bias condition for the first gate, the second gate, and the third gate to provide a selection signal to one of the plurality of memory cells, wherein the bias condition comprises zero volts for the first gate, the second gate, and the third gate for a positive configuration for the memory cells and a negative voltage for the third gate and zero volts for the first gate and the second gate for a negative configuration for the memory cells.

公开(公告)号：US20230395145A1

公开(公告)日：2023-12-07

申请号：US17831311

申请日：2022-06-02

Applicant: Micron Technology, Inc.

Inventor： Vijayakrishna J. Vankayala ,  Hari Giduturi ,  Jeffrey E. Koelling ,  Mingdong Cui ,  Ramachandra Rao Jogu

IPC: G11C13/00

CPC classification number: G11C13/0023 ,  G11C13/0004 ,  H03K19/20

Abstract: The present disclosure includes apparatuses, methods, and systems for pre-decoder circuitry. An embodiment includes a memory array including a plurality of memory cells, decoder circuitry coupled to the memory array, wherein the decoder circuitry comprises a p-type transistor having a first gate, a first n-type transistor having a second gate, and a second n-type transistor having a third gate, and pre-decoder circuitry configured to provide a bias condition for the first gate, the second gate, and the third gate to provide a selection signal to one of the plurality of memory cells, wherein the bias condition comprises zero volts for the first gate, the second gate, and the third gate for a positive configuration for the memory cells and a negative voltage for the third gate and zero volts for the first gate and the second gate for a negative configuration for the memory cells.