公开(公告)号：US20250130937A1

公开(公告)日：2025-04-24

申请号：US18781982

申请日：2024-07-23

Applicant: Micron Technology, Inc.

Inventor： Rishabh Dubey

IPC: G06F12/02

Abstract: A system including a memory device and an operatively coupled processing device to perform operations determining a size of a minimum allocation unit (MAU) for a plurality of logical devices, dividing the memory device into logical units with a size equal to the MAU, identifying, using a logical device identifier (LDI) data structure, a first LDI that is available, wherein the first LDI identifies a first logical device, identifying, using a logical unit identifier (LUI) data structure, a first set of LUI that are available, wherein the first set of LUI identify a first set of logical units, allocating the first set of logical units to the first logical device, and updating an LDI-to-LUI mapping data structure to reflect that the first set of logical units are allocated to the first logical device.

公开(公告)号：US20250094343A1

公开(公告)日：2025-03-20

申请号：US18782147

申请日：2024-07-24

Applicant: Micron Technology, Inc.

Inventor： Rishabh Dubey ,  Marco Sforzin ,  Emanuele Confalonieri ,  Danilo Caraccio ,  Daniele Balluchi ,  Nicola Del Gatto

IPC: G06F12/02 ,  G06F13/16

Abstract: A variety of applications can include a memory device having dynamic page mapping with compression. The memory device can include a mapping table having an entry location to associate a virtual page with a physical address of a first stripe of data of the virtual page. The entry location can include a flag along with the physical address of the first stripe. The flag can identify data of the virtual page as being compressed or uncompressed. A controller of the memory device, responsive to the flag identifying the data of virtual page being compressed, is structured to generate a format of compressed data of the first stripe with a header. The header can include a count of additional physical addresses to store compressed data of the virtual page and the additional physical addresses. Additional apparatus, systems, and methods are disclosed.

公开(公告)号：US20250094047A1

公开(公告)日：2025-03-20

申请号：US18782539

申请日：2024-07-24

Applicant: Micron Technology, Inc.

Inventor： Marco Sforzin ,  Rishabh Dubey ,  Daniele Balluchi ,  Danilo Caraccio ,  Emanuele Confalonieri ,  Nicola Del Gatto

IPC: G06F3/06

Abstract: A variety of applications can include a memory device implementing a dual compression scheme. A memory subsystem of the memory device can be arranged into multiple regions. A first region of the memory subsystem can be used to store non-compressible data. A second region can be used to store compressible data. The second region can have a first subregion and a second subregion. The first subregion can be used to accept compressible data as non-compressed data corresponding to a compression ratio being less than a threshold compression ratio. The second subregion can be used to accept compressed data corresponding to a compression ratio being greater than the threshold compression ratio. Additional apparatus, systems, and methods are disclosed.

公开(公告)号：US20250094344A1

公开(公告)日：2025-03-20

申请号：US18782380

申请日：2024-07-24

Applicant: Micron Technology, Inc.

Inventor： Rishabh Dubey ,  Marco Sforzin ,  Emanuele Confalonieri ,  Danilo Caraccio ,  Daniele Balluchi ,  Nicola Del Gatto

IPC: G06F12/02 ,  G06F13/16

Abstract: A variety of applications can include a memory device having chained mapping with compression of received data. The memory device can include a mapping table having an entry location to associate a virtual page with a physical address of a first stripe of compressed data of the virtual page. A controller of the memory device, responsive to the data of the virtual page being compressed data, can load information about a second stripe of the compressed data into extra locations in the first stripe different from locations for compressed data of the virtual page in the first stripe. Additional apparatus, systems, and methods are disclosed.