公开(公告)号：US12131783B2

公开(公告)日：2024-10-29

申请号：US17540752

申请日：2021-12-02

Applicant: Micron Technology, Inc.

Inventor： Xiangyu Yang ,  Ching-Huang Lu

IPC: G11C16/34 ,  G11C16/04 ,  G11C16/08 ,  G11C16/26

CPC classification number: G11C16/08 ,  G11C16/0483 ,  G11C16/26 ,  G11C16/3427

Abstract: A memory device includes a memory array and control logic, operatively coupled with the memory array, to perform operations including initiating a read recovery process associated with a block of the memory array. The block includes wordlines at an initial voltage. The operations further include causing an early discharge sequence to be performed on a first set of wordlines of the wordlines during the read recovery process to alleviate latent read disturb. The early discharge sequence includes ramping the first set of wordlines from the initial voltage to a ramping voltage while maintaining a second set of wordlines of the wordlines at the initial voltage.

公开(公告)号：US20230024346A1

公开(公告)日：2023-01-26

申请号：US17591361

申请日：2022-02-02

Applicant: Micron Technology, Inc.

Inventor： Xiangyu Yang ,  Hong-Yan Chen ,  Ching-Huang Lu

IPC: G11C16/26 ,  G11C16/10 ,  G11C16/04 ,  G11C16/24 ,  G11C16/08 ,  G11C16/30

Abstract: A memory device includes unselected sub-block, which includes bit line; drain select (SGD) transistor coupled with bit line; a source voltage line; source select (SGS) transistor coupled with source voltage; and wordlines coupled with gates of string of cells, which have channel coupled between the SGS/SGD transistors. Control logic coupled with unselected sub-block is to: cause the SGD/SGS transistors to turn on while ramping the wordlines from a ground voltage to a pass voltage associated with unselected wordlines in preparation for read operation; cause, while ramping the wordlines, the channel to be pre-charged by ramping voltages on the bit line and the source voltage line to a target voltage that is greater than a source read voltage level; and in response to wordlines reaching the pass voltage, causing the SGD and SGS transistors to be turned off, to leave the channel pre-charged to the target voltage during the read operation.

公开(公告)号：US20220392530A1

公开(公告)日：2022-12-08

申请号：US17540752

申请日：2021-12-02

Applicant: Micron Technology, Inc.

Inventor： Xiangyu Yang ,  Ching-Huang Lu

IPC: G11C16/08 ,  G11C16/04 ,  G11C16/26 ,  G11C16/34

Abstract: A memory device includes a memory array and control logic, operatively coupled with the memory array, to perform operations including initiating a read recovery process associated with a block of the memory array. The block includes wordlines at an initial voltage. The operations further include causing an early discharge sequence to be performed on a first set of wordlines of the wordlines during the read recovery process to alleviate latent read disturb. The early discharge sequence includes ramping the first set of wordlines from the initial voltage to a ramping voltage while maintaining a second set of wordlines of the wordlines at the initial voltage.

公开(公告)号：US20250022513A1

公开(公告)日：2025-01-16

申请号：US18903353

申请日：2024-10-01

Applicant: Micron Technology, Inc.

Inventor： Xiangyu Yang ,  Ching-Huang Lu

IPC: G11C16/08 ,  G11C16/04 ,  G11C16/26 ,  G11C16/34

Abstract: A memory device includes a memory array and control logic, operatively coupled with the memory array, to perform operations including identifying a plurality of wordlines at an initial voltage different from a pass-through voltage, and causing an early discharge sequence to be performed with respect to the plurality of wordlines. The early discharge sequence includes ramping at least a first set of wordlines of the plurality of wordlines from the initial voltage to a ramping voltage different from the pass-through voltage.

公开(公告)号：US20250037773A1

公开(公告)日：2025-01-30

申请号：US18781618

申请日：2024-07-23

Applicant: Micron Technology, Inc.

Inventor： Ching-Huang Lu ,  Xiangyu Yang ,  Yingda Dong

IPC: G11C16/26 ,  G11C11/56 ,  G11C16/04 ,  G11C16/08

Abstract: Apparatuses, systems, and methods for applying a read voltage overdrive. One example apparatus can include an array of memory cells and a controller coupled to the array of memory cells, wherein the controller is configured to apply a pass voltage to a wordline in the array of memory cells, apply a read voltage to the wordline, and apply a read voltage overdrive greater than the read voltage and less than or equal to the pass voltage to the wordline.

公开(公告)号：US20240248637A1

公开(公告)日：2024-07-25

申请号：US18412010

申请日：2024-01-12

Applicant: Micron Technology, Inc.

Inventor： Go Shikata ,  Xiangyu Yang ,  Ching-Huang Lu

IPC: G06F3/06

CPC classification number: G06F3/0655 ,  G06F3/0604 ,  G06F3/0679

Abstract: A memory device can include a memory array coupled with control logic. The control logic initiates a read operation on one or more memory cells of a plurality of memory cells arranged in one or more tiers. The control logic can further cause a read voltage to be applied to a selected wordline coupled to the one or more memory cells during the read operation. The control logic can cause a first voltage to be applied to a first set of unselected wordlines coupled to memory cells in a first tier of the one or more tiers during the read operation. The control logic can cause a second voltage to be applied to a second set of unselected wordlines coupled to memory cells in a second tier of the one or more tiers during the read operation, wherein the second voltage is less than the first voltage.

公开(公告)号：US11894069B2

公开(公告)日：2024-02-06

申请号：US17591361

申请日：2022-02-02

Applicant: Micron Technology, Inc.

Inventor： Xiangyu Yang ,  Hong-Yan Chen ,  Ching-Huang Lu

IPC: G11C16/04 ,  G11C16/26 ,  G11C16/10 ,  G11C16/30 ,  G11C16/24 ,  G11C16/08

CPC classification number: G11C16/26 ,  G11C16/0433 ,  G11C16/08 ,  G11C16/102 ,  G11C16/24 ,  G11C16/30

Abstract: A memory device includes unselected sub-block, which includes bit line; drain select (SGD) transistor coupled with bit line; a source voltage line; source select (SGS) transistor coupled with source voltage; and wordlines coupled with gates of string of cells, which have channel coupled between the SGS/SGD transistors. Control logic coupled with unselected sub-block is to: cause the SGD/SGS transistors to turn on while ramping the wordlines from a ground voltage to a pass voltage associated with unselected wordlines in preparation for read operation; cause, while ramping the wordlines, the channel to be pre-charged by ramping voltages on the bit line and the source voltage line to a target voltage that is greater than a source read voltage level; and in response to wordlines reaching the pass voltage, causing the SGD and SGS transistors to be turned off, to leave the channel pre-charged to the target voltage during the read operation.