公开(公告)号：US20090218679A1

公开(公告)日：2009-09-03

申请号：US12437817

申请日：2009-05-08

Applicant: Min-Chih Hsuan ,  Kai-Kuang Ho ,  Kuo-Ming Chen ,  Kuang-Hui Tang

Inventor： Min-Chih Hsuan ,  Kai-Kuang Ho ,  Kuo-Ming Chen ,  Kuang-Hui Tang

IPC: H01L23/538

CPC classification number: H01L23/04 ,  H01L21/481 ,  H01L21/4846 ,  H01L23/3114 ,  H01L23/481 ,  H01L23/49805 ,  H01L23/552 ,  H01L24/02 ,  H01L27/14618 ,  H01L2224/0401 ,  H01L2224/16 ,  H01L2924/01013 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01075 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/12042 ,  H01L2924/14 ,  H01L2924/15311 ,  H01L2924/16195 ,  H01L2924/16235 ,  H01L2924/00

Abstract: A chip package is disclosed. The chip package comprises a chip, a plurality of bond pads, a plurality of connecting lines and a rigid cover. The chip has a plurality of recesses arranged along at least an edge of the chip and also has an active surface and a backside. The bond pads are disposed on the active surface and the bond pads are arranged to be corresponding to the recesses respectively. The connecting lines are disposed on surfaces of the recesses respectively at the edge of the chip. For each of the connecting lines, a first end of the connecting line is connected to one of the bond pads and a second end of the connecting line extends to the backside to be a terminal pad. The rigid cover is located on the active surface without covering the bond pads on the active surface.

Abstract translation: 公开了一种芯片封装。 芯片封装包括芯片，多个接合焊盘，多个连接线和刚性盖。 芯片具有沿着芯片的至少边缘布置的多个凹槽，并且还具有有源表面和背面。 接合焊盘设置在有源表面上，并且接合焊盘分别布置成对应于凹部。 连接线分别设置在芯片的边缘处的凹部的表面上。 对于每个连接线，连接线的第一端连接到一个接合焊盘，并且连接线的第二端延伸到背面以作为端子焊盘。 刚性盖位于活动表面上，而不覆盖活动表面上的接合垫。

公开(公告)号：US07192847B2

公开(公告)日：2007-03-20

申请号：US10906136

申请日：2005-02-04

Applicant: Min-Chih Hsuan

Inventor： Min-Chih Hsuan

IPC: H01L21/44 ,  H01L21/48 ,  H01L21/50 ,  H01L21/301 ,  H01L21/46

CPC classification number: H01L25/50 ,  H01L23/3114 ,  H01L25/0657 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A method of forming an ultra-thin wafer level stack package and structure thereof are provided. The method includes providing a first wafer having a plurality of base chips thereon, selectively binding the first wafer to a second substrate, lapping the first wafer to reduce its thickness, dicing the lapped first wafer, bonding a plurality stack chips to each base chip and packaging the base chip with the bonded stack chips to form an IC package. Thus, each IC package comprises at least a base chip and a stack chip. The IC package has a size almost identical to the base chip and a thickness a little larger than the combined thickness of the base chip and the stack chip. If a known good die inspection of the base chips and stack chips are carried out prior to wafer level packaging, overall yield of the IC package is increased.

Abstract translation: 提供了一种形成超薄晶片级堆叠封装的方法及其结构。 该方法包括提供其上具有多个基底芯片的第一晶片，选择性地将第一晶片连接到第二基板，研磨第一晶片以减小其厚度，切割重叠的第一晶片，将多个堆叠芯片结合到每个基底芯片，以及 将基片与封装的堆叠芯片封装形成IC封装。 因此，每个IC封装至少包括基片和堆叠片。 IC封装的尺寸几乎与基片相同，厚度稍大于基片和叠片芯片的组合厚度。 如果在晶片级封装之前进行基片和堆叠芯片的已知的良好的裸片检查，则IC封装的总产量增加。

公开(公告)号：US20050088517A1

公开(公告)日：2005-04-28

申请号：US10700785

申请日：2003-11-03

Applicant: Min-Chih Hsuan

Inventor： Min-Chih Hsuan

IPC: H01L29/00 ,  H04N5/225 ,  H04N7/18

CPC classification number: H04N5/2254 ,  H04N5/335

Abstract: An integrated audio/video sensor is provided. The integrated sensor comprises an image-receiving module for sensing a light of an image, a sound-receiving module for sensing a sound and a signal-transforming module for integrating image and sound signals into an audio/video signal. The integrated sensor integrates image and sound together simultaneously and synchronously. Furthermore, the integrated sensor can be connected directly to an image-processing system. The integrated sensor not only provides excellent synchronization of audio and video signals, but also reduces the size and cost of producing the integrated sensor as well.

Abstract translation: 提供集成的音频/视频传感器。 集成传感器包括用于感测图像的光的图像接收模块，用于感测声音的声音接收模块和用于将图像和声音信号集成到音频/视频信号中的信号变换模块。 集成传感器将图像和声音同时并入同步。 此外，集成传感器可以直接连接到图像处理系统。 该集成传感器不仅提供音频和视频信号的卓越同步，而且还降低了生成集成传感器的尺寸和成本。

公开(公告)号：US08976018B2

公开(公告)日：2015-03-10

申请号：US13431437

申请日：2012-03-27

Applicant: Min-Chih Hsuan

Inventor： Min-Chih Hsuan

IPC: G08B19/00

CPC classification number: G08B19/00

Abstract: A local detection processing system includes a local detection processing device and at least two types of detectors. The detectors are disposed in an area for detecting properties or property changes of a specific target to generate a detection signal. The local detection processing device analyzes the detection signals and transmits the detection result to a processing center. The local detection processing device includes a detection information receiving unit receiving the detection signals generated by the at least two types of detectors; a memory unit recording codes of the at least two types of detectors, a format of the detection signal, information of the corresponding processing center and values of the detection signals; an information processing unit analyzing the received detection signals, determining a detection result whether to transmit the detection result and the processing center; and a communication unit connecting at least two processing centers.

Abstract translation: 本地检测处理系统包括本地检测处理装置和至少两种类型的检测器。 检测器设置在用于检测特定目标的属性或属性变化的区域中以产生检测信号。 本地检测处理装置分析检测信号，并将检测结果发送到处理中心。 本地检测处理装置包括：检测信息接收单元，接收由至少两种类型的检测器产生的检测信号; 记录所述至少两种检测器的代码的记录单元，检测信号的格式，相应的处理中心的信息和检测信号的值; 分析接收到的检测信号的信息处理单元，确定是否发送检测结果和处理中心的检测结果; 以及连接至少两个处理中心的通信单元。

公开(公告)号：US08786427B2

公开(公告)日：2014-07-22

申请号：US13431413

申请日：2012-03-27

Applicant: Min-Chih Hsuan

Inventor： Min-Chih Hsuan

IPC: G08B1/08

CPC classification number: G08B25/14

Abstract: A portable information detection and processing device includes an information detection unit, for detecting information recorded by at least one functional element; a memory unit, for recording recognition data of the at least one functional element and information detected by the functional element; a display unit, for displaying the recognition data of the functional element and the information recorded by the functional element; and an information processing unit, connected to the information detection unit, the memory unit and the display unit, for processing the recognition data of the functional element and the information detected by the functional element, and controlling the information detection unit, the memory unit and the display unit.

Abstract translation: 便携式信息检测处理装置包括：信息检测单元，用于检测由至少一个功能元件记录的信息; 用于记录所述至少一个功能元件的识别数据和由所述功能元件检测的信息的存储器单元; 显示单元，用于显示功能元件的识别数据和由功能元件记录的信息; 以及信息处理单元，连接到信息检测单元，存储单元和显示单元，用于处理功能元件的识别数据和由功能元件检测的信息，并且控制信息检测单元，存储单元和 显示单元。

公开(公告)号：US20060065976A1

公开(公告)日：2006-03-30

申请号：US10711536

申请日：2004-09-24

Applicant: Min-Chih Hsuan ,  Paul Chen ,  Hermen Liu ,  Kun-Chih Wang ,  Kai-Kuang Ho

Inventor： Min-Chih Hsuan ,  Paul Chen ,  Hermen Liu ,  Kun-Chih Wang ,  Kai-Kuang Ho

IPC: H01L23/48

CPC classification number: H01L24/97 ,  H01L23/15 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/49816 ,  H01L24/48 ,  H01L24/73 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/05001 ,  H01L2224/05026 ,  H01L2224/05568 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05666 ,  H01L2224/13111 ,  H01L2224/16225 ,  H01L2224/2929 ,  H01L2224/293 ,  H01L2224/32225 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/73265 ,  H01L2224/8121 ,  H01L2224/81815 ,  H01L2224/97 ,  H01L2924/00011 ,  H01L2924/00014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01049 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/01322 ,  H01L2924/09701 ,  H01L2924/10253 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/351 ,  H01L2224/81 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/29075 ,  H01L2224/83851 ,  H01L2224/05099 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207

Abstract: The present invention relates to a method for manufacturing a wafer level chip scale package structure including the following steps. After providing a glass substrate and a wafer comprising a plurality of chips, the active surface of the wafer is connected to the top surface of the glass substrate. The wafer is connected with the glass substrate through either bumps or pads thereon. After drilling the glass substrate to form a plurality of through holes, a plating process is performed to form a plurality of via plugs in the through holes. Afterwards, a singulation step is performed and a plurality of chip scale package structures is obtained.

Abstract translation: 本发明涉及一种晶片级芯片级封装结构的制造方法，包括以下步骤。 在提供玻璃基板和包括多个芯片的晶片之后，晶片的有效表面连接到玻璃基板的顶表面。 晶片通过其上的凸块或焊盘与玻璃基板连接。 在钻出玻璃基板以形成多个通孔之后，进行电镀工艺以在通孔中形成多个通孔塞。 之后，进行分割步骤，并获得多个芯片级封装结构。

公开(公告)号：US20050099587A1

公开(公告)日：2005-05-12

申请号：US10704396

申请日：2003-11-06

Applicant: Min-Chih Hsuan

Inventor： Min-Chih Hsuan

IPC: G02F1/13 ,  G02F1/1335

CPC classification number: G02F1/1309 ,  G02F1/133526 ,  G02F2201/508

Abstract: A method of repairing white spots on a liquid crystal display (LCD) panel and a LCD pane thereof are provided. The method includes the steps of detecting any white spot on the liquid crystal display after the manufacturing process and repairing the white spot by coating a repairing spot on the surface of the panel above the white spot. Furthermore, the repairing spot may have a micro-lens structure. Therefore, the repairing spot can absorb, diverge or scatter the light from the white spot. Alternatively, the repairing spot can also change the optical pathway or the polarity or the polarity distribution of the light from the white spot so that an analyzer or a polarizer can block the light from the white spot to produce a dark spot.

Abstract translation: 提供了在液晶显示器（LCD）面板及其LCD面板上修复白点的方法。 该方法包括以下步骤：在制造过程之后检测液晶显示器上的任何白点，并通过在白点上方的面板表面上涂覆修复点来修复白点。 此外，修复点可以具有微透镜结构。 因此，修复点可以吸收，分散或散布来自白点的光。 或者，修复点也可以改变来自白点的光的光路或极性或极性分布，使得分析器或偏振器可以阻挡来自白点的光以产生暗斑。

公开(公告)号：US06268642B1

公开(公告)日：2001-07-31

申请号：US09299706

申请日：1999-04-26

Applicant: Min-Chih Hsuan ,  Cheng-Te Lin

Inventor： Min-Chih Hsuan ,  Cheng-Te Lin

IPC: H01L23544

CPC classification number: H01L25/0657 ,  H01L23/3114 ,  H01L24/05 ,  H01L24/13 ,  H01L24/16 ,  H01L24/48 ,  H01L2224/05022 ,  H01L2224/05556 ,  H01L2224/05558 ,  H01L2224/13016 ,  H01L2224/13027 ,  H01L2224/13099 ,  H01L2224/131 ,  H01L2224/16105 ,  H01L2224/16106 ,  H01L2224/16157 ,  H01L2224/16227 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/85447 ,  H01L2924/00014 ,  H01L2924/00015 ,  H01L2924/01005 ,  H01L2924/01022 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01075 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/04941 ,  H01L2924/10253 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/15153 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/30105 ,  H01L2924/30107 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2224/85399 ,  H01L2224/05599 ,  H01L2224/13 ,  H01L2924/00012 ,  H01L2224/45099 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/014

Abstract: A wafer level package structure. The method of forming the wafer level package structure includes covering a silicon chip having a plurality of integrated circuit devices thereon with an insulation layer. Next, a plurality of bonding pads is formed on the periphery of the silicon chip above the insulation layer. The bonding pads are formed such that each bonding pad is electrically connected to the terminal of an integrated circuit device. Thereafter, a passivation layer is deposited over the insulation layer and the bonding pads, and then openings that expose a portion of the bonding pad are formed. Subsequently, a metallic layer is formed on the sidewalls and the exposed bonding pad area. The metallic layer also extends over the passivation layer in the neighborhood of the opening and towards the edge of the wafer chip. Next, a layer of packaging material is deposited over the passivation layer. Finally, a metallic bump is formed over the exposed metallic layer lying above each opening.

Abstract translation: 晶圆级封装结构。 形成晶片级封装结构的方法包括用绝缘层覆盖其上具有多个集成电路器件的硅芯片。 接下来，在绝缘层上方的硅芯片的周围形成多个接合焊盘。 接合焊盘形成为使得每个接合焊盘电连接到集成电路器件的端子。 此后，在绝缘层和接合焊盘上沉积钝化层，然后形成露出接合焊盘的一部分的开口。 随后，在侧壁和暴露的焊盘区域上形成金属层。 金属层还在开口附近并朝向晶片芯片的边缘的钝化层上延伸。 接下来，在钝化层上沉积一层包装材料。 最后，在位于每个开口上方的暴露的金属层上形成金属凸块。

公开(公告)号：US06252300B1

公开(公告)日：2001-06-26

申请号：US09260218

申请日：1999-03-01

Applicant: Min-Chih Hsuan ,  Charlie Han

Inventor： Min-Chih Hsuan ,  Charlie Han

IPC: H01L2302

CPC classification number: H01L25/50 ,  H01L21/76898 ,  H01L23/481 ,  H01L24/11 ,  H01L24/48 ,  H01L25/0657 ,  H01L2224/02166 ,  H01L2224/05001 ,  H01L2224/05085 ,  H01L2224/05567 ,  H01L2224/05572 ,  H01L2224/05599 ,  H01L2224/13022 ,  H01L2224/13099 ,  H01L2224/14181 ,  H01L2224/16 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2224/48137 ,  H01L2224/48247 ,  H01L2224/73257 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2924/00014 ,  H01L2924/01005 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01022 ,  H01L2924/01024 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2924/01046 ,  H01L2924/01074 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/04941 ,  H01L2924/1305 ,  H01L2924/13091 ,  H01L2924/14 ,  H01L2924/181 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/3011 ,  H01L2924/00 ,  H01L2224/45015 ,  H01L2924/207 ,  H01L2924/00012 ,  H01L2224/45099

Abstract: A direct contact through hole type wafer structure. Both sides of a wafer have devices and contacts. The contacts are coupled with the devices. Bumps are formed on the contacts, respectively.

Abstract translation: 直接接触通孔型晶片结构。 晶片的两侧都有器件和触点。 触点与设备耦合。 分别在触点上形成凸起。

公开(公告)号：US6166444A

公开(公告)日：2000-12-26

申请号：US337708

申请日：1999-06-21

Applicant: Min-Chih Hsuan ,  Charlie Han

Inventor： Min-Chih Hsuan ,  Charlie Han

IPC: H01L25/065 ,  H01L23/485 ,  H01L23/52 ,  H01L23/522 ,  H01L29/40

CPC classification number: H01L25/0652 ,  H01L24/13 ,  H01L2224/05008 ,  H01L2224/05024 ,  H01L2224/05027 ,  H01L2224/0508 ,  H01L2224/05166 ,  H01L2224/05171 ,  H01L2224/05572 ,  H01L2224/48091 ,  H01L2924/00014 ,  H01L2224/05639 ,  H01L2224/05644 ,  H01L2224/05647 ,  H01L2224/05655 ,  H01L2224/05664 ,  H01L2224/05147 ,  H01L2924/01029 ,  H01L2924/01074 ,  H01L2924/01028 ,  H01L2924/013

Abstract: A cascade-type chip module. A laminate substrate having contacts is provided. Chips suitable for the cascade-type module are provided. Each chip includes a redistribution layer having a first region and a second region and bump contacts over the redistribution layer. A layout of the bump contacts coupling with the first region of the redistribution layer is an image rotationally symmetrical to the layout of those coupling with the second region of the redistribution layer, and each of the bump contacts coupling with the first region is coupled with a corresponding bump contact coupling with the second region through the redistribution layer. The chips are divided into a first group and a second group; the first group is stacked on the second group such that the first region of each chip of the first group is aligned with the second region of each chip of the second group and the second region of each chip of the first group is aligned with the first region of each chip of the second group. The chips are coupled to each other by bumps. The chips are attached to the laminate substrate and the first group and the second group are respectively coupled with the contacts by two film carriers.

Abstract translation: 级联型芯片模块。 提供具有触点的层叠基板。 提供了适用于级联型模块的芯片。 每个芯片包括具有第一区域和第二区域的再分配层，并且凸块接触再分布层上方。 与再分布层的第一区域耦合的突起触点的布局是与再分布层的第二区域耦合的布局的布局旋转对称的图像，并且与第一区域耦合的每个凸起触点与 通过再分布层与第二区域相应的凸起接触。 芯片分为第一组和第二组; 第一组堆叠在第二组上，使得第一组的每个芯片的第一区域与第二组的每个芯片的第二区域对准，并且第一组的每个芯片的第二区域与第一组的第一组对准 第二组的每个芯片的区域。 芯片通过凸块相互耦合。 芯片附接到层叠基板，第一组和第二组分别通过两个薄膜载体与触点耦合。