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公开(公告)号：US11797841B2
公开(公告)日：2023-10-24
申请号：US16357438
申请日：2019-03-19
Inventor： Shinichi Ouchi , Hiroshi Fuketa
Abstract: A computing system capable of obtaining a calculation speed exceeding that of 16-bit floating point processing while maintaining accuracy of calculation results. A computing system includes a parameter server, a communication path and a worker. The parameter server has a storage unit that stores a parameter value of a training target model, and a first conversion unit that converts the parameter value into data represented by a floating point number with 10 bits or less. The communication path transmits the data transmitted and received between the parameter server and the worker. The worker has a processing unit that computes a product and a sum of the data. The parameter server further has a second conversion unit that converts the data with 10 bits or less received from the worker into an updating difference, and an updating unit that updates the parameter value on the basis of the updating difference.
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公开(公告)号：US20190019766A1
公开(公告)日：2019-01-17
申请号：US15750614
申请日：2016-08-03
Inventor： Yohei Hori , Yongxun Liu , Shinichi Ouchi , Tetsuji Yasuda , Meishoku Masahara , Toshifumi Irisawa , Kazuhiko Endo , Hiroyuki Ota , Tatsuro Maeda , Hanpei Koike , Yasuhiro Ogasahara , Toshihiro Katashita , Koichi Fukuda
IPC: H01L23/00 , H01L25/065 , H01L23/522
Abstract: A semiconductor device 100 of the present invention includes a front end and back ends A and B, each including a plurality of layers. Further, in the plurality of layers of the back end B, (i) circuits 22, 23, and 24 having a security function are provided in at least one layer having a wiring pitch of 100 nm or more, (ii) a circuit having a security function is provided in at least one wiring layer in M5 or higher level (M5, M6, M7, . . . ), (iii) a circuit having a security function is provided in at least one layer, for which immersion ArF exposure does not need to be used, or (iv) a circuit having a security function is provided in at least one layer that is exposed by using an exposure wavelength of 200 nm or more.
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公开(公告)号：US09584079B2
公开(公告)日：2017-02-28
申请号：US14648775
申请日：2013-12-03
Inventor： Shinichi Ouchi
CPC classification number: H03F3/393 , H03F3/005 , H03F3/45179 , H03F3/45192 , H03F3/45475 , H03F2200/168 , H03F2200/249 , H03F2200/271 , H03F2200/405 , H03F2203/45366 , H03F2203/45512 , H03F2203/45544 , H03F2203/7212
Abstract: There is provided an operational amplifier which is operable as well when an operating voltage decreases without creating a range where a circuit would not operate or reducing circuit gain. High-pass filters 102-105 provide output signals therefrom to bias-set input nodes of differential amplifiers Gm1-Gm4 to a potential within a common-mode range in which the respective differential amplifiers Gm1-Gm4 are operable. In this manner, the respective differential amplifiers Gm1-Gm4 can be operated effectively regardless of the possible decrease in a supply voltage, enabling normal amplifying operation. In addition, reduction in gain due to the reduced operational voltage is avoided. Therefore, it is preferably applicable to the application where digital and analog circuits are loaded together on the same IC chip. When a high-pass filter is required at each input side of two- or more-stage differential amplifiers, a phase compensation method utilizing multiple paths is provided for a lower range of a phase margin created at the low frequency side, enabling normal amplitude operation.
Abstract translation: 提供了一种运算放大器，当工作电压降低而不产生电路不工作的范围或降低电路增益时，该放大器也可操作。 高通滤波器102-105将差分放大器Gm1-Gm4的偏置设置输入节点的输出信号提供给各个差分放大器Gm1-Gm4可操作的共模范围内的电位。 以这种方式，可以有效地操作各个差分放大器Gm1-Gm4，而不管可能的电源电压降低，从而能够进行正常的放大操作。 此外，避免了由于降低的操作电压而导致的增益的降低。 因此，优选地适用于同一IC芯片上数字和模拟电路一起加载的应用。 当在两级或更多级差分放大器的每个输入侧需要高通滤波器时，为低频侧产生的相位余量的较低范围提供利用多路径的相位补偿方法，使得能够进行正常幅度运算 。
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