公开(公告)号：US20190173457A1

公开(公告)日：2019-06-06

申请号：US15828618

申请日：2017-12-01

Applicant: NOVATEK MICROELECTRONICS CORP.

Inventor： Chien-Chuan Huang ,  Chia-Hsin Tung ,  Chun-Hung Chen ,  Hao-Jan Yang ,  Chieh-Hsiang Chang

IPC: H03K5/00 ,  H03K5/135 ,  G09G3/20 ,  G09G5/18 ,  H03K5/131 ,  G09G5/00

CPC classification number: H03K5/00006 ,  G06F1/10 ,  G09G3/2096 ,  G09G5/005 ,  G09G5/18 ,  H03K5/131 ,  H03K5/135

Abstract: A display driving circuit, a calibration module, and an associated calibration method are provided. The display driving circuit includes an internal clock circuit and the calibration module. The internal clock circuit generates an internal clock signal. The calibration module includes a counting circuit and a trimming circuit. The counting circuit counts pulses of a reference clock signal to generate a detected reference-clock count and counts pulses of the internal clock signal to generate a detected internal-clock count. The trimming circuit generates a calibration signal to adjust frequency of the internal clock signal when a predefined condition is satisfied. The predefined condition is related to comparison between a first preset count and one of the detected reference-clock count and the detected internal-clock count.

公开(公告)号：US10355679B2

公开(公告)日：2019-07-16

申请号：US15828618

申请日：2017-12-01

Applicant: NOVATEK MICROELECTRONICS CORP.

Inventor： Chien-Chuan Huang ,  Chia-Hsin Tung ,  Chun-Hung Chen ,  Hao-Jan Yang ,  Chieh-Hsiang Chang

IPC: H03K5/00 ,  H03K5/131 ,  H03K5/135 ,  G09G3/20 ,  G09G5/00 ,  G09G5/18 ,  G09F1/10 ,  G06F1/10

Abstract: A display driving circuit, a calibration module, and an associated calibration method are provided. The display driving circuit includes an internal clock circuit and the calibration module. The internal clock circuit generates an internal clock signal. The calibration module includes a counting circuit and a trimming circuit. The counting circuit counts pulses of a reference clock signal to generate a detected reference-clock count and counts pulses of the internal clock signal to generate a detected internal-clock count. The trimming circuit generates a calibration signal to adjust frequency of the internal clock signal when a predefined condition is satisfied. The predefined condition is related to comparison between a first preset count and one of the detected reference-clock count and the detected internal-clock count.