公开(公告)号：US11573854B2

公开(公告)日：2023-02-07

申请号：US17523775

申请日：2021-11-10

Applicant: NVIDIA CORPORATION

Inventor： Gautam Bhatia ,  Robert Bloemer ,  Sunil Rao Sudhakaran

IPC: G06F11/10 ,  G06F3/06

Abstract: Various embodiments include a memory device that recovers from write errors and read errors more quickly relative to prior memory devices. Certain patterns of write data and read data may result on poor signal quality on the memory interface between memory controllers and memory devices. The disclosed memory device, synchronously with the memory controller, scrambles read data before transmitting the data to the memory controller and descrambles received from the memory controller. The scrambling and descrambling results in a different pattern on the memory interface even for the same read data or write data. Therefore, when a write operation or a read operation fails, and the operation is replayed, the pattern transmitted on the memory interface is different when the operation is replayed. As a result, the memory device more easily recovers from data patterns that cause poor signal quality on the memory interface.

公开(公告)号：US12298845B2

公开(公告)日：2025-05-13

申请号：US18070006

申请日：2022-11-28

Applicant: NVIDIA CORPORATION

Inventor： Gautam Bhatia

IPC: G06F11/10 ,  G06F11/07

Abstract: Various embodiments include a memory device that recovers from write errors and read errors more quickly relative to prior memory devices. Certain patterns of write data and read data may result on poor signal quality on the memory interface between memory controllers and memory devices. The disclosed memory device, synchronously with the memory controller, scrambles read data before transmitting the data to the memory controller and descrambles received from the memory controller. The scrambling and descrambling results in a different pattern on the memory interface even for the same read data or write data. Therefore, when a write operation or a read operation fails, and the operation is replayed, the pattern transmitted on the memory interface is different when the operation is replayed. As a result, the memory device more easily recovers from data patterns that cause poor signal quality on the memory interface.

公开(公告)号：US20140185633A1

公开(公告)日：2014-07-03

申请号：US13730556

申请日：2012-12-28

Applicant: NVIDIA CORPORATION

Inventor： Peter C. Mills ,  Gautam Bhatia

IPC: H04L7/00

CPC classification number: H04L7/0037 ,  H04L7/0337

Abstract: One embodiment provides a data-receiving device component comprising a phase shifter, timer logic, and control logic. The phase shifter is configured to release a train of clock pulses with a controlled phase shift. The timer logic is configured to receive data from a data-sending device, and for each transition of the data received, to determine whether a clock pulse from the train is early or late with respect to the transition, and to tally the late clock pulses relative to the early clock pulses. The control logic, operatively coupled to the phase shifter and to the timer logic, is configured to incrementally advance the phase shift when the late clock pulses outnumber the early clock pulses by a non-integer power of two.

Abstract translation: 一个实施例提供了包括移相器，定时器逻辑和控制逻辑的数据接收设备组件。 移相器被配置为释放具有受控相移的一串时钟脉冲。 定时器逻辑被配置为从数据发送设备接收数据，并且对于接收到的数据的每个转换，以确定来自列车的时钟脉冲是否相对于转换的早期或晚期，并且对晚时钟脉冲进行计数 相对于早期的时钟脉冲。 可操作地耦合到移相器和定时器逻辑的控制逻辑被配置为当后期时钟脉冲超过早期时钟脉冲的非整数倍数为2时，递增地推进相移。

公开(公告)号：US12142344B2

公开(公告)日：2024-11-12

申请号：US17959586

申请日：2022-10-04

Applicant: NVIDIA CORPORATION

Inventor： Gautam Bhatia

IPC: G11C7/10 ,  G11C7/22

Abstract: Various embodiments include a memory device that is capable of performing memory access operations with reduced power consumption relative to prior approaches. The memory device receives early indication as to whether a forthcoming memory access operation is a read operation or a write operation. The memory device enables various circuits and disables other circuits depending on whether this early indication identifies an upcoming memory access operation as a read operation or a write operation. As a result, circuits that are not needed for an upcoming memory access operation are disabled earlier during the memory access operation relative to prior approaches. Disabling such circuits earlier during the memory access operation reduces power consumption without reducing memory device performance.

公开(公告)号：US11861229B2

公开(公告)日：2024-01-02

申请号：US17523780

申请日：2021-11-10

Applicant: NVIDIA CORPORATION

Inventor： Robert Bloemer ,  Gautam Bhatia

IPC: G06F3/06 ,  G11C7/10

CPC classification number: G06F3/0659 ,  G06F3/0604 ,  G06F3/0679

Abstract: Various embodiments include a memory device that is capable of transferring both commands and data via a single clock signal input. In order to initialize the memory device to receive commands, a memory controller transmits a synchronization command to the memory device. The synchronization command establishes command start points that identify the beginning clock cycle of a command that is transferred to the memory device over multiple clock cycles. Thereafter, the memory controller transmits subsequent commands to the memory device according to a predetermined command length. The predetermined command length is based on the number of clock cycles needed to transfer each command to the memory device. Adjacent command start points are separated from one another by the predetermined command length. In this manner, the memory device avoids the need for a second lower speed clock signal for transferring commands to the memory device.

公开(公告)号：US11809719B2

公开(公告)日：2023-11-07

申请号：US17550811

申请日：2021-12-14

Applicant: NVIDIA CORPORATION

Inventor： Gautam Bhatia ,  Robert Bloemer

IPC: G06F3/06

CPC classification number: G06F3/0619 ,  G06F3/0659 ,  G06F3/0673

Abstract: Various embodiments include a memory device that is capable of performing write training operations. Prior approaches for write training involve storing a long data pattern into the memory followed by reading the long data pattern to determine whether the data was written to memory correctly. Instead, the disclosed memory device stores a first data pattern (e.g., in a FIFO memory within the memory device) or generates the first data pattern (e.g., using PRBS) that is compared with a second data pattern being transmitted to the memory device by an external memory controller. If data patterns match, then the memory device stores a pass status in a register, otherwise a fail status is stored in the register. The memory controller reads the register to determine whether the write training passed or failed.

公开(公告)号：US11742007B2

公开(公告)日：2023-08-29

申请号：US17523779

申请日：2021-11-10

Applicant: NVIDIA CORPORATION

Inventor： Gautam Bhatia ,  Robert Bloemer

IPC: G11C7/10 ,  G11C7/20 ,  H03K19/21

CPC classification number: G11C7/109 ,  G11C7/1063 ,  G11C7/20 ,  H03K19/21

Abstract: Various embodiments include a memory device that is capable of performing write training operations, to determine that certain timing conditions are met, without storing data patterns in memory. Prior approaches for write training involve storing a long data pattern into the memory followed by reading the long data pattern to determine whether the data was written to memory correctly. Instead, the disclosed memory device generates a data pattern within the memory device that matches the data pattern being transmitted to the memory device by an external memory controller. If the data pattern generated by the memory device matches the data pattern received from the memory controller, then the memory device stores a pass status in a register. If the data patterns do not match, then the memory device stores a pass status in a register. The memory controller reads the register to determine whether the write training passed or failed.

公开(公告)号：US11742006B2

公开(公告)日：2023-08-29

申请号：US17523778

申请日：2021-11-10

Applicant: NVIDIA CORPORATION

Inventor： Robert Bloemer ,  Gautam Bhatia

IPC: G11C7/10 ,  H03K19/21

CPC classification number: G11C7/109 ,  G11C7/1036 ,  G11C7/1063 ,  H03K19/21

Abstract: Various embodiments include a memory device that is capable of performing command address interface training operations, to determine that certain timing conditions are met, with fewer I/O pins relative to prior approaches. Prior approaches for command address interface training involve loading data via a set of input pins, a clock signal, and a clock enable signal that identifies when the input pins should be sampled. Instead, the disclosed memory device generates a data pattern within the memory device that matches the data pattern continuously being transmitted to the memory device by an external memory controller. The memory device compares the generated data pattern with the received data pattern and transmits the result of the comparison on one or more data output pins. The memory controller receives and analyzes the result of the comparison to determine whether the command address interface training passed or failed.

公开(公告)号：US09762381B2

公开(公告)日：2017-09-12

申请号：US13935391

申请日：2013-07-03

Applicant: NVIDIA CORPORATION

Inventor： Lizhi Zhong ,  Vishnu Balan ,  Gautam Bhatia

IPC: H04L7/00 ,  H04L25/03 ,  H04L7/033

CPC classification number: H04L7/0087 ,  H04L7/0025 ,  H04L7/0058 ,  H04L7/033 ,  H04L25/03057 ,  H04L2025/03484 ,  H04L2025/03605

Abstract: A method comprises receiving an input signal at an input of a receiver and retrieving a data sample signal and an error sample signal from the input signal. The method also comprises applying an adaptive procedure to generate a feedback code using the data sample signal and the error sample signal for feeding back into a decision feedback equalization (DFE) module. Further, it comprises converting the feedback code into a corresponding voltage value and assigning the corresponding voltage value as a tap weight for the DFE module. Finally, it comprises generating an edge sample signal by applying DFE to the input signal using the DFE module, wherein the DFE is based on the tap weight.

公开(公告)号：US09184907B2

公开(公告)日：2015-11-10

申请号：US13730556

申请日：2012-12-28

Applicant: NVIDIA Corporation

Inventor： Peter C. Mills ,  Gautam Bhatia

IPC: H04L7/00

CPC classification number: H04L7/0037 ,  H04L7/0337

Abstract: One embodiment provides a data-receiving device component comprising a phase shifter, timer logic, and control logic. The phase shifter is configured to release a train of clock pulses with a controlled phase shift. The timer logic is configured to receive data from a data-sending device, and for each transition of the data received, to determine whether a clock pulse from the train is early or late with respect to the transition, and to tally the late clock pulses relative to the early clock pulses. The control logic, operatively coupled to the phase shifter and to the timer logic, is configured to incrementally advance the phase shift when the late clock pulses outnumber the early clock pulses by a non-integer power of two.

Abstract translation: 一个实施例提供了包括移相器，定时器逻辑和控制逻辑的数据接收设备组件。 移相器被配置为释放具有受控相移的一串时钟脉冲。 定时器逻辑被配置为从数据发送设备接收数据，并且对于接收到的数据的每个转换，以确定来自列车的时钟脉冲是否相对于转换的早期或晚期，并且对晚时钟脉冲进行计数 相对于早期的时钟脉冲。 可操作地耦合到移相器和定时器逻辑的控制逻辑被配置为当后期时钟脉冲超过早期时钟脉冲的非整数倍数为2时，递增地推进相移。