公开(公告)号：US20210382834A1

公开(公告)日：2021-12-09

申请号：US17403832

申请日：2021-08-16

Applicant: Netlist, Inc.

Inventor： Jefferey C. Solomon ,  Jayesh R. Bhakta

IPC: G06F13/16 ,  G11C5/04 ,  G06F13/00 ,  G06F12/00 ,  G06F13/42 ,  G11C7/10 ,  G11C15/00

Abstract: A memory module operable to communicate data with a memory controller via a memory bus. The memory module comprises memory devices and logic configurable to receive and register a set of input address and control signals associated with a read or write memory command and to output data transfer control signals. The memory module further comprises circuitry coupled between the memory bus and the memory devices. The circuitry is configurable to be in any of a plurality of states including a first state and a second state, and to transition from the first state to the second state in response to the data transfer control signals. The circuitry in the first state is configured to disable signal communication through the circuitry. The circuitry in the second state is configured to transfer the data signals associated with the read or write command in accordance with a transfer time budget of the memory module.

公开(公告)号：US11093417B2

公开(公告)日：2021-08-17

申请号：US16695020

申请日：2019-11-25

Applicant: Netlist, Inc.

Inventor： Jefferey C. Solomon ,  Jayesh R. Bhakta

IPC: G06F12/00 ,  G06F13/16 ,  G11C5/04 ,  G06F13/00 ,  G06F13/42 ,  G11C7/10 ,  G11C15/00

Abstract: A memory module operable to communicate data with a memory controller via a N-bit wide memory bus comprises memory devices arranged in a plurality of N-bit wide ranks. The memory module further comprises logic configurable to receive a set of input address and control signals associated with a read or write memory command and output registered address and control signals and data buffer control signals. The memory module further comprises circuitry coupled between the memory bus and corresponding data pins of memory devices in each of the plurality of N-bit wide ranks. The circuitry is configurable to enable registered transfers of N-bit wide data signals associated with the memory read or write command between the N-bit wide memory bus and the memory devices in response to the data buffer control signals and in accordance with an overall CAS latency of the memory module, which is greater than an actual operational CAS latency of the memory devices.

公开(公告)号：US12222878B2

公开(公告)日：2025-02-11

申请号：US17403832

申请日：2021-08-16

Applicant: Netlist, Inc.

Inventor： Jefferey C. Solomon ,  Jayesh R. Bhakta

IPC: G06F13/16 ,  G06F12/00 ,  G06F13/00 ,  G06F13/42 ,  G11C5/04 ,  G11C7/10 ,  G11C15/00

Abstract: A memory module operable to communicate data with a memory controller via a memory bus. The memory module comprises memory devices and logic configurable to receive and register a set of input address and control signals associated with a read or write memory command and to output data transfer control signals. The memory module further comprises circuitry coupled between the memory bus and the memory devices. The circuitry is configurable to be in any of a plurality of states including a first state and a second state, and to transition from the first state to the second state in response to the data transfer control signals. The circuitry in the first state is configured to disable signal communication through the circuitry. The circuitry in the second state is configured to transfer the data signals associated with the read or write command in accordance with a transfer time budget of the memory module.

公开(公告)号：US09037774B2

公开(公告)日：2015-05-19

申请号：US13971231

申请日：2013-08-20

Applicant: Netlist, Inc.

Inventor： Jefferey C. Solomon ,  Jayesh R. Bhakta

IPC: G06F12/00 ,  G11C5/04 ,  G06F13/00

CPC classification number: G06F13/1673 ,  G06F12/00 ,  G06F13/00 ,  G06F13/4243 ,  G06F13/4282 ,  G11C5/04 ,  G11C7/1072 ,  G11C15/00

Abstract: A memory module includes a plurality of memory devices and is operable in a computer system to perform memory operations in response to memory commands from a memory controller of the computer system. The memory module comprises a register device configured to receive a set of input control/address signals associated with a respective memory command (e.g., a read command or a write command) from the memory controller and to generate a set of output control/address signals in response to the set of input control/address signals. The set of output control/address signals are provided to the plurality of memory devices. The memory module further comprises a circuit to selectively isolate one or more first memory devices among the plurality of memory devices from the memory controller in response to the respective memory command so as to reduce a load of the memory module to the computer system while one or more second memory devices among the plurality of memory devices are communicating with the memory controller in response to the set of output control/address signals.

Abstract translation: 存储器模块包括多个存储器设备，并且可在计算机系统中操作以响应于来自计算机系统的存储器控​​制器的存储器命令来执行存储器操作。 存储器模块包括寄存器装置，其被配置为从存储器控制器接收与相应存储器命令（例如，读取命令或写入命令）相关联的一组输入控制/地址信号，并且生成一组输出控制/地址信号 响应于该组输入控制/地址信号。 输出控制/地址信号组被提供给多个存储器件。 存储器模块还包括电路，用于响应于相应的存储器命令，选择性地将多个存储器件中的一个或多个第一存储器件与存储器控制器隔离开来，以便将存储器模块的负载减小到计算机系统，同时， 响应于该组输出控制/地址信号，多个存储器件中的更多的第二存储器件正在与存储器控制器进行通信。

公开(公告)号：US20140040569A1

公开(公告)日：2014-02-06

申请号：US13971231

申请日：2013-08-20

Applicant: Netlist, Inc.

Inventor： Jefferey C. Solomon ,  Jayesh R. Bhakta

IPC: G06F12/00

CPC classification number: G06F13/1673 ,  G06F12/00 ,  G06F13/00 ,  G06F13/4243 ,  G06F13/4282 ,  G11C5/04 ,  G11C7/1072 ,  G11C15/00

Abstract: A circuit is mountable on a memory module that includes a plurality of memory devices and that is operable in a computer system to perform memory operations in response to memory commands from a memory controller. The circuit comprises a register device configured to receive a set of input control/address signals associated with a respective memory command (e.g., a read command or a write command) from the memory controller and to generate a set of output control/address signals in response to the set of input control/address signals. The set of output control/address signals are provided to the plurality of memory devices. The circuit further comprises logic to monitor the memory commands from the memory controller and to selectively isolate one or more first memory devices among the plurality of memory devices from the memory controller in response to the respective memory command so as to reduce a load of the memory module to the computer system while one or more second memory devices among the plurality of memory devices are communicating with the memory controller in response to the set of output control/address signals.

Abstract translation: 电路可安装在包括多个存储器设备的存储器模块上，并且可在计算机系统中操作以响应于来自存储器控制器的存储器命令执行存储器操作。 电路包括寄存器装置，其被配置为从存储器控制器接收与相应存储器命令相关联的一组输入控制/地址信号（例如，读取命令或写入命令），并且生成一组输出控制/地址信号 响应一组输入控制/地址信号。 输出控制/地址信号组被提供给多个存储器件。 该电路还包括用于监视来自存储器控制器的存储器命令的逻辑，并且响应于相应的存储器命令，选择性地将多个存储器件中的一个或多个第一存储器件与存储器控制器隔离，以便减少存储器的负载 模块连接到计算机系统，而多个存储器件中的一个或多个第二存储器件响应于该组输出控制/地址信号而与存储器控制器进行通信。