公开(公告)号：US10083152B1

公开(公告)日：2018-09-25

申请号：US13749114

申请日：2013-01-24

Applicant: OPEN INVENTION NETWORK LLC

Inventor： Russell C. McKown

IPC: G06F9/44 ,  G06F15/76 ,  G06F9/4401 ,  G06F9/30

CPC classification number: G06F15/76 ,  G06F9/30138 ,  G06F9/30181 ,  G06F9/3885 ,  G06F9/4405 ,  G06F9/45533 ,  G06F9/5088 ,  G06F15/80 ,  G06T1/20 ,  Y02D10/26

Abstract: A system on a chip may include a plurality of data plane processor cores sharing a common instruction set architecture. At least one of the data plane processor cores is specialized to perform a particular function via extensions to the otherwise common instruction set architecture. Such systems on a chip may have reduced physical complexity, cost, and time-to-market, and may provide improvements in core utilization and reductions in system power consumption.

公开(公告)号：US10659534B1

公开(公告)日：2020-05-19

申请号：US15949426

申请日：2018-04-10

Applicant: OPEN INVENTION NETWORK LLC

Inventor： Russell C. McKown

IPC: G06F9/46 ,  H04L29/08

Abstract: Disclosed are an apparatus and method of operating and allocating a shared memory between various applications operating via a processing computing platform. One example may include receiving a first buffer context switch request message from a first application operating via a processor, transmitting a first buffer context switch flag to the processor operating the application confirming the first buffer context switch request was received, receiving a second buffer context switch request from a second application with a different processing cycle operating via the processor and transmitting a second buffer context switch flag to the processor operating the second application confirming the second buffer context switch request was received. Once the applications have been identified and confirmed, a synchronization operation may be performed to create a shared number of memory units between at least two different buffers and provide the shared memory units to the first application and the second application.

公开(公告)号：US10318083B1

公开(公告)日：2019-06-11

申请号：US15689146

申请日：2017-08-29

Applicant: OPEN INVENTION NETWORK LLC

Inventor： Russell C. McKown ,  David Gerard Ledet

IPC: G06F3/044 ,  G06F3/01

Abstract: The present invention provides a module or system and a method that includes: 1) a transparent screen assembly containing an actuator layer lying between two layers of transparent multiple line electrodes, where one electrode layer of forms lines in the x-direction layer and the other electrode layer forms lines in the y-direction; and 2) a controller that is connected to these electrodes. The system and method of the present invention provides: 1) multiple touch sensing on or near a surface of the transparent screen and 2) simultaneous high resolution tactile feedback across the same surface.

公开(公告)号：US09942327B1

公开(公告)日：2018-04-10

申请号：US14987423

申请日：2016-01-04

Applicant: OPEN INVENTION NETWORK LLC

Inventor： Russell C. McKown

IPC: G06F9/46 ,  H04L29/08

CPC classification number: H04L67/1097 ,  G06F9/461 ,  G06F12/10 ,  G06F2212/1016 ,  G06F2212/152 ,  G06F2212/656 ,  H04L67/28

Abstract: Disclosed are an apparatus and method of operating and allocating a shared memory between various applications operating via a processing computing platform. One example may include receiving a first buffer context switch request message from a first application operating via a processor, transmitting a first buffer context switch flag to the processor operating the application confirming the first buffer context switch request was received, receiving a second buffer context switch request from a second application with a different processing cycle operating via the processor and transmitting a second buffer context switch flag to the processor operating the second application confirming the second buffer context switch request was received. Once the applications have been identified and confirmed, a synchronization operation may be performed to create a shared number of memory units between at least two different buffers and provide the shared memory units to the first application and the second application.

公开(公告)号：US11106623B1

公开(公告)日：2021-08-31

申请号：US16780990

申请日：2020-02-04

Applicant: OPEN INVENTION NETWORK LLC

Inventor： Russell C. McKown

IPC: G06F9/44 ,  G06F15/76 ,  G06F9/455 ,  G06F9/50 ,  G06F9/38 ,  G06F9/30 ,  G06F15/80 ,  G06T1/20 ,  G06F9/4401

Abstract: A system on a chip may include a plurality of data plane processor cores sharing a common instruction set architecture. At least one of the data plane processor cores is specialized to perform a particular function via extensions to the otherwise common instruction set architecture. Such systems on a chip may have reduced physical complexity, cost, and time-to-market, and may provide improvements in core utilization and reductions in system power consumption.

公开(公告)号：US10552369B1

公开(公告)日：2020-02-04

申请号：US16137527

申请日：2018-09-20

Applicant: Open Invention Network LLC

Inventor： Russell C. McKown

IPC: G06F9/44 ,  G06F15/76 ,  G06F9/455 ,  G06F9/38 ,  G06T1/20 ,  G06F15/80 ,  G06F9/4401 ,  G06F9/30

Abstract: A system on a chip may include a plurality of data plane processor cores sharing a common instruction set architecture. At least one of the data plane processor cores is specialized to perform a particular function via extensions to the otherwise common instruction set architecture. Such systems on a chip may have reduced physical complexity, cost, and time-to-market, and may provide improvements in core utilization and reductions in system power consumption.

公开(公告)号：US10324658B1

公开(公告)日：2019-06-18

申请号：US15390624

申请日：2016-12-26

Applicant: OPEN INVENTION NETWORK LLC

Inventor： Russell C. McKown

IPC: G06F3/00 ,  G06F3/06

Abstract: Disclosed are an apparatus and method of operating and allocating a shared memory between various applications operating via a processing computing platform. One example may include receiving a first buffer context switch request message from a first application operating via a processor, transmitting a first buffer context switch flag to the processor operating the application confirming the first buffer context switch request was received, receiving a second buffer context switch request from a second application with a different processing cycle operating via the processor and transmitting a second buffer context switch flag to the processor operating the second application confirming the second buffer context switch request was received. Once the applications have been identified and confirmed, a synchronization operation may be performed to create a shared number of memory units between at least two different buffers and provide the shared memory units to the first application and the second application.

公开(公告)号：US09965287B1

公开(公告)日：2018-05-08

申请号：US13749044

申请日：2013-01-24

Applicant: Open Invention Network LLC

Inventor： Russell C. McKown

IPC: G06F9/45 ,  G06F9/38 ,  G06F9/30 ,  G06F9/44 ,  G06T1/20 ,  G06F15/80

CPC classification number: G06F9/3885 ,  G06F9/30138 ,  G06F9/30181 ,  G06F9/4405 ,  G06F9/45533 ,  G06F15/80 ,  G06T1/20

Abstract: A system on a chip may include a plurality of data plane processor cores sharing a common instruction set architecture. At least one of the data plane processor cores is specialized to perform a particular function via extensions to the otherwise common instruction set architecture. Such systems on a chip may have reduced physical complexity, cost, and time-to-market, and may provide improvements in core utilization and reductions in system power consumption.