Abstract:
An internal device (1) is implanted in a living body (300). A control section (6) causes a communication section (5) to wirelessly transmit data corresponding to electroencephalogram signals of the living body (300) which are detected through a group of N (N is 2 or more) electrodes, to an external device (200). When the communication section (5) receives a designation signal designating a group of M electrode(s) (2a), M being smaller than N, the communication section (5) is caused to transmit data corresponding to electroencephalogram signals of the living body (300) which are detected through the group of M electrode(s) (2a), to the external device (200) in real time.
Abstract:
A mattress 100 includes a movable part 1 and a mattress body 2 including a first mattress part 21 disposed above the movable part 1, and a second mattress part 22 provided separately from the first mattress part 21 and disposed to surround the first mattress part in a plan view. The first mattress part 21 is configured to rotate upward about the predetermined rotation axis by the movable part 1.
Abstract:
To allow an implantable device including an electronic circuit to be implanted in the head in a more preferable manner in terms of appearance and safely. This implantable device is used for a brain-machine interface or the like. A casing of an implantable device configured to be implanted in a human head has an outer convexity surface matching an external shape of a resected skull related to at least a craniotomy site of the artificial bone designed in accordance with a skull shape of each person in order to fill the craniotomy site. That is, the outer convexity surface of the artificial bone is provided with two functions: the original function of filling the craniotomy site as the artificial bone and a function of serving as the casing of the implantable device.
Abstract:
A resistance device (100) includes a field-effect transistor (TN) and a voltage applying circuit (1). The voltage applying circuit (1) applies a control voltage (Vgs) between the gate and source of the field-effect transistor (TN) according to a temperature (T) to control a resistance value (R) between the drain and source of the field-effect transistor (TN). The control voltage (Vgs) is a voltage obtained by adding a correction voltage (Vc) to a reference voltage (Vgs0). The correction voltage (Vc) depends on the temperature (T) and is set to be zero at a first temperature (T1).