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    DIGITAL-ANALOG MEMORY INTEGRATED DEEP LEARNING ACCELERATOR SYSTEM AND ARTIFICIAL NEURAL NETWORK LEARNING METHOD USING THE SAME
    1.
    发明申请
    DIGITAL-ANALOG MEMORY INTEGRATED DEEP LEARNING ACCELERATOR SYSTEM AND ARTIFICIAL NEURAL NETWORK LEARNING METHOD USING THE SAME 有权

    公开(公告)号：US20250077854A1

    公开(公告)日：2025-03-06

    申请号：US18652689

    申请日：2024-05-01

    Applicant: POSTECH RESEARCH AND BUSINESS DEVELOPMENT FOUNDATION

    Inventor： Seyoung KIM ,  Doyoon KIM

    IPC: G06N3/065 ,  G06N3/08

    Abstract: A digital-analog memory integrated deep learning accelerator system may include: a main digital device including a first array, the first array having digital circuits and configured to store weights for on-chip learning; an analog device including a second array, the second array having analog circuits and configured to update and store gradient information about the weights during the on-chip learning; and a sub-digital device including a third array, the third array having digital circuits and configured to store values read from the second array and to transfer a value exceeding a threshold to the first array. The digital-analog memory integrated deep learning accelerator system may perform a matrix-level learning process through an array set including the first array, the second array, and the third array. An artificial neural network learning method for a digital-analog memory integrated deep learning accelerator system is also disclosed.

    NEUROMORPHIC SEMICONDUCTOR DEVICE AND OPERATING METHOD THEREOF
    4.
    发明申请
    NEUROMORPHIC SEMICONDUCTOR DEVICE AND OPERATING METHOD THEREOF 有权

    公开(公告)号：US20250157556A1

    公开(公告)日：2025-05-15

    申请号：US18945134

    申请日：2024-11-12

    Applicant: POSTECH RESEARCH AND BUSINESS DEVELOPMENT FOUNDATION

    Inventor： Seyoung KIM ,  Byoungwoo LEE

    IPC: G11C27/00

    Abstract: The present disclosure relates to a neuromorphic semiconductor device and an operation method thereof, and a resistive processing unit used as a synaptic element includes a first N-type metal oxide semiconductor (NMOS) transistor electrically connected to a first input terminal, a second NMOS transistor electrically connected to a second input terminal and connected in series with the first NMOS transistor, and a read transistor connected to the second NMOS transistor and configured to store charge and read the amount of stored charge.

    DEVICE-BASED CROSS POINT ARRAY AND METHOD OF OPERATION THEREOF
    5.
    发明申请
    DEVICE-BASED CROSS POINT ARRAY AND METHOD OF OPERATION THEREOF 有权

    公开(公告)号：US20250140313A1

    公开(公告)日：2025-05-01

    申请号：US18758245

    申请日：2024-06-28

    Applicant: POSTECH RESEARCH AND BUSINESS DEVELOPMENT FOUNDATION

    Inventor： Seyoung KIM ,  Byoungwoo LEE

    IPC: G11C13/00

    Abstract: Disclosed a device-based cross point array and a method of operation therefor. The method relates to a method for updating a cross point array implemented as a device where a potentiation region and a depression region are separated, and the method is performed by a control logic. The method includes: in a first cycle, controlling lines where positive values are applied among first lines, in ON state, and applying a first voltage pulse at each of second lines intersecting with the first lines based on an applied value; and in a second cycle, controlling lines where negative values are applied among the first lines, in ON state, and applying a second voltage pulse at each of the second lines based on an applied value.

    SYNAPTIC ARRAY DEVICE AND ARTIFICIAL NEURAL NETWORK LEARNING METHOD USING IT
    6.
    发明公开
    SYNAPTIC ARRAY DEVICE AND ARTIFICIAL NEURAL NETWORK LEARNING METHOD USING IT 审中-公开

    公开(公告)号：US20240220784A1

    公开(公告)日：2024-07-04

    申请号：US18381273

    申请日：2023-10-18

    Applicant: POSTECH Research and Business Development Foundation

    Inventor： Seyoung KIM ,  Doyoon KIM

    IPC: G06N3/063

    CPC classification number: G06N3/063

    Abstract: A synaptic array device according to one embodiment of the present disclosure comprises a first synaptic array representing weight values, a second synaptic array receiving the error gradient of the weights of the first synaptic array and representing gradient values refined in row units, and a third synaptic array receiving the gradient values refined in row units from the second synaptic array and passing the portion of the received gradient values exceeding a threshold to the first synaptic array, wherein the third synaptic array derives a moving average value by averaging accumulated values of the gradient values received from the second synaptic array and passes the derived moving average value to the second synaptic array.

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