公开(公告)号：US20190074185A1

公开(公告)日：2019-03-07

申请号：US16103025

申请日：2018-08-14

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Hidehiko KARASAKI ,  Noriyuki MATSUBARA ,  Atsushi HARIKAI ,  Hidefumi SAEKI

IPC: H01L21/3065 ,  B23K26/0622 ,  H01L21/67 ,  H01L21/02 ,  H01L21/475

Abstract: Method of manufacturing an element chip which can suppress residual debris in plasma dicing. A back surface of a semiconductor wafer is held on a dicing tape. Then, a surface of the wafer is coated with a mask that includes a water-insoluble lower mask and a water-soluble upper mask. Subsequently, an opening is formed in the mask by irradiating the mask with laser light to expose a dividing region. Then, the semiconductor wafer is caused to come into contact with water to remove the upper mask covering each of the element regions while leaving the lower layer. After that, the wafer is exposed to plasma to perform etching on the dividing region exposed from the opening until the etching reaches the back surface, thereby dicing the semiconductor wafer into a plurality of element chips. Thereafter, the lower layer mask left on the front surface of the semiconductor chips is removed.

公开(公告)号：US20240162091A1

公开(公告)日：2024-05-16

申请号：US18501124

申请日：2023-11-03

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Hidehiko KARASAKI ,  Shogo OKITA ,  Toshiyuki TAKASAKI ,  Ryota FURUKAWA

IPC: H01L21/78 ,  H01L21/308

CPC classification number: H01L21/78 ,  H01L21/3086 ,  H01L21/3065

Abstract: The disclosed element chip manufacturing method includes: a first step of imparting hydrophilicity to a first surface 11 of a substrate 1, the first surface 11 including element regions 11A and dicing regions 11B defining the element regions 11A; a second step of applying a raw material liquid containing a water-soluble resin onto the first surface 11, to form a water-soluble resin layer 20 on the first surface 11; a third step of applying a laser beam to the water-soluble resin layer 20 covering the dicing regions 11B, to form openings 20a that expose the dicing regions 11B, in the water-soluble resin layer 20; a fourth step of etching the dicing regions 11B exposed at the openings 20a, with plasma, to obtain element chips 30; and a fifth step of removing the water-soluble resin layer 20 by bringing the element chips 30 into contact with a water-containing cleaning liquid.

公开(公告)号：US20220384177A1

公开(公告)日：2022-12-01

申请号：US17663452

申请日：2022-05-16

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Hidehiko KARASAKI ,  Shogo OKITA

IPC: H01L21/02 ,  H01L21/68 ,  H01L21/463

Abstract: A method including: a step of preparing a substrate that includes a first layer having a first principal surface provided with a dicing region, and a mark, and a second principal surface, and includes a semiconductor layer; a step of covering a first region corresponding to the mark on the second principal surface, with a resist film; a step of forming a metal film on the second principal surface; a step of removing the resist film, to expose the semiconductor layer corresponding to the first region; a step of imaging the substrate, with a camera, to detect a position of the mark through the semiconductor layer, and calculating a second region corresponding to the dicing region on a surface of the metal film; and a step of irradiating a laser beam to the second region, to remove the metal film and expose the semiconductor layer corresponding to the second region.

公开(公告)号：US20220406660A1

公开(公告)日：2022-12-22

申请号：US17806367

申请日：2022-06-10

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Shogo OKITA ,  Hidehiko KARASAKI ,  Hidefumi SAEKI ,  Atsushi HARIKAI

IPC: H01L21/78 ,  H01L21/268

Abstract: An element chip manufacturing method includes a step of preparing a substrate including a semiconductor layer and a wiring layer formed on the semiconductor layer and having a plurality of element regions and a dicing region defining the element regions, a laser grooving step of irradiating a laser beam to the wiring layer at the dicing region, to form an aperture exposing the semiconductor layer, and an individualization step of etching the semiconductor layer exposed from the aperture, with plasma, to divide the substrate into a plurality of element chips. The laser grooving step including a step of irradiating a first laser beam, to form a first groove exposing the semiconductor layer in the dicing region, and a step of irradiating a second laser beam, with a beam center positioned outside a side wall of the first groove, to widen the first groove into the aperture.

公开(公告)号：US20220402072A1

公开(公告)日：2022-12-22

申请号：US17806360

申请日：2022-06-10

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Hidefumi SAEKI ,  Hidehiko KARASAKI ,  Shogo OKITA ,  Atsushi HARIKAI ,  Akihiro ITOU

IPC: B23K26/364 ,  B23K26/40 ,  H01L21/78 ,  H01L21/3065 ,  B23K26/0622

Abstract: An element chip manufacturing method includes a step of preparing a substrate including a semiconductor layer and a wiring layer formed on the semiconductor layer, the substrate having element regions and a dicing region defining the element regions, a laser grooving step of irradiating a laser beam to the wiring layer at the dicing region, to form an aperture exposing the semiconductor layer, and a step of etching the semiconductor layer exposed from the aperture, with plasma, to divide the substrate into a plurality of element chips. The laser grooving step includes a step of irradiating a first laser beam having a first pulse width, to remove the wiring layer in an edge portion of the dicing region, and a step of irradiating a second laser beam having a second pulse width which is longer than the first pulse width, to remove the wiring layer inside from the edge portion.

公开(公告)号：US20220367273A1

公开(公告)日：2022-11-17

申请号：US17661584

申请日：2022-05-02

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Hidehiko KARASAKI ,  Shogo OKITA

IPC: H01L21/78 ,  H01L23/544

Abstract: A method including: a step of preparing a substrate that includes a first layer having a dicing region and a mark, and including a semiconductor layer, and a second layer including a metal film; a step of removing the metal film, to expose the semiconductor layer corresponding to a first region that corresponds to the mark; a step of smoothing a surface of the exposed semiconductor layer; a step of imaging the substrate, with a camera sensing predetermined electromagnetic waves, to detect a position of the mark through the semiconductor layer, and calculating a second region corresponding to the dicing region; and a step of removing the metal film, to expose the semiconductor layer corresponding to the second region. In the smoothing step, the surface of the semiconductor layer is smoothed so as to have a surface roughness of 1/4 or less of a wavelength of the predetermined electromagnetic waves.

公开(公告)号：US20190006238A1

公开(公告)日：2019-01-03

申请号：US16008280

申请日：2018-06-14

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Noriyuki MATSUBARA ,  Hidehiko KARASAKI

IPC: H01L21/82 ,  H01L21/683 ,  H01L21/3065 ,  H01L21/67 ,  H01L21/308 ,  B23K26/364

CPC classification number: H01L21/82 ,  B23K26/0622 ,  B23K26/08 ,  B23K26/364 ,  B23K26/402 ,  B23K2101/40 ,  B23K2103/172 ,  B23K2103/42 ,  B23K2103/56 ,  H01L21/30655 ,  H01L21/3081 ,  H01L21/67069 ,  H01L21/67207 ,  H01L21/6833 ,  H01L21/6836 ,  H01L21/78 ,  H01L2221/68327

Abstract: Provided is a manufacturing process of an element chip, which comprises a preparing step for preparing a substrate containing element regions and dicing regions, a holding step for holding the substrate and a frame with a holding sheet, an applicating step for applying a resin material solution containing a resin constituent and a solvent on the substrate to form a coated layer containing the resin constituent and the solvent thereon, a heating step for heating the substrate held on the holding sheet through a heat shielding member shielding the frame and the holding sheet to substantially remove the solvent from the coated layer, thereby to form a resin layer, a patterning step for patterning the resin layer to expose the substrate in the dicing regions, and a dicing step for dicing the substrate into element chips by plasma-etching the substrate.

公开(公告)号：US20180174908A1

公开(公告)日：2018-06-21

申请号：US15811733

申请日：2017-11-14

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Hidehiko KARASAKI ,  Hidefumi SAEKI ,  Atsushi HARIKAI

IPC: H01L21/78 ,  H01L21/268

CPC classification number: H01L21/78 ,  B23K26/0622 ,  B23K26/364 ,  B23K26/402 ,  B23K2101/40 ,  B23K2103/172 ,  B23K2103/56 ,  H01J37/32 ,  H01L21/2686 ,  H01L21/30655

Abstract: A manufacturing process of an element chip comprises a preparation step for preparing a substrate, the substrate including first and second streets crossing each other to define a plurality of element regions. Also, it comprises a first shallow-groove formation step for radiating a laser beam along the first streets to form a plurality of first shallow grooves being shallower than a thickness of the substrate, a second shallow-groove formation step for radiating the laser beam along the second streets to form a plurality of second shallow grooves being shallower than a thickness of the substrate, a first groove formation step for radiating the laser beam along the first shallow grooves to form a plurality of first grooves, and a plasma dicing step for etching the substrate along the first grooves and the second shallow grooves by a plasma exposure to dice the substrate into a plurality of element chips.

公开(公告)号：US20240312841A1

公开(公告)日：2024-09-19

申请号：US18602117

申请日：2024-03-12

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： Hidefumi SAEKI ,  Hidehiko KARASAKI ,  Shogo OKITA ,  Toshiyuki TAKASAKI ,  Akihiro ITOU

IPC: H01L21/78 ,  B23K26/36 ,  H01L21/56 ,  H01L21/683

CPC classification number: H01L21/78 ,  B23K26/36 ,  H01L21/561 ,  H01L21/568 ,  H01L21/6836 ,  H01L2221/68327

Abstract: An element chip manufacturing method disclosed herein includes a preparation process of preparing a substrate having a semiconductor layer, a wiring layer, a plurality of element areas and a dividing area, a resin layer formation process of forming a resin layer covering the wiring layer, an opening formation process of irradiating the wiring layer and the resin layer in the dividing area to form an opening in which the semiconductor layer is exposed in the dividing area, a reflow process of reducing the opening by reflowing the resin layer, and a singulation process of dividing the substrate into a plurality of element chips each including a different one of the element areas, by performing etching of the substrate with plasma along the opening reduced in the reflow process, using the resin layer as a mask.

公开(公告)号：US20210324226A1

公开(公告)日：2021-10-21

申请号：US17280185

申请日：2020-03-09

Applicant: GOO CHEMICAL CO., LTD. ,  Panasonic Intellectual Property Management Co., Ltd.

Inventor： Teru SAKAKIBARA ,  Shinya KOMABIKI ,  Koji MAEDA ,  Hidehiko KARASAKI

IPC: C09D167/02 ,  C08G63/189 ,  C08G63/183 ,  H01L21/683 ,  H01L21/78

Abstract: A protective composition contains a water-soluble polyester resin including a polyvalent carboxylic acid residue and a polyvalent alcohol residue. The polyvalent carboxylic acid residue includes: a polyvalent carboxylic acid residue having a metal sulfonate group; and a naphthalene dicarboxylic acid residue. The proportion of the polyvalent carboxylic acid residue to the polyvalent carboxylic acid residue falls within the range from 25 mol % to 70 mol %. The proportion of the naphthalene dicarboxylic acid residue to the polyvalent carboxylic acid residue falls within the range from 30 mol % to 75 mol %.