公开(公告)号：US07109749B2

公开(公告)日：2006-09-19

申请号：US10449750

申请日：2003-05-29

Applicant: Namerita Khanna ,  Parvesh Swami ,  Deepak Agarwal

Inventor： Namerita Khanna ,  Parvesh Swami ,  Deepak Agarwal

IPC: H03K19/177

CPC classification number: H03K19/1776 ,  H03K3/012 ,  H03K3/037 ,  H03K19/1737 ,  H03K19/17728 ,  H03K19/17784

Abstract: A Programmable Logic Device providing reduction in power consumption for sequential logic and data storage functions, including at least one circuit arrangement configurable to function as a dual-edge-triggered flip-flop operating on a selected one or both edges of the circuit clock.

Abstract translation: 一种可编程逻辑器件，用于为顺序逻辑和数据存储功能提供功率消耗降低，包括至少一个电路装置，其可配置为在电路时钟选定的一个或两个边缘上工作的双边沿触发触发器。

公开(公告)号：US20060120141A1

公开(公告)日：2006-06-08

申请号：US11254558

申请日：2005-10-20

Applicant: Anoop Khurana ,  Parvesh Swami

Inventor： Anoop Khurana ,  Parvesh Swami

IPC: G11C11/00

CPC classification number: G11C7/1051 ,  G11C7/106 ,  G11C7/1078 ,  G11C7/1087 ,  G11C11/419 ,  H03K19/1776 ,  H03K19/17776 ,  H03K19/17792

Abstract: A configuration memory structure includes one or more distributed buffers cascaded together, the output of a first buffer driving an output data line and complementary output data line which terminate at the input of a succeeding buffer. The first buffer includes precharging elements connected between a source and the data line and complementary data line, respectively; data sensing and holding elements connected between respective input and complementary input data lines and the data line and complementary data line, respectively; and tristate elements connected to the outputs of the data sensing and holding elements. This scheme provides fast and reliable configuration and configuration read back, especially for a high density FPGA.

Abstract translation: 配置存储器结构包括级联在一起的一个或多个分布式缓冲器，驱动输出数据线的第一缓冲器的输出和终止于后续缓冲器的输入端的互补输出数据线。 第一缓冲器包括分别连接在源与数据线和互补数据线之间的预充电元件; 数据传感和保持元件分别连接在相应的输入和互补输入数据线以及数据线和互补数据线之间; 并连接到数据传感和保持元件的输出的三态元件。 该方案提供快速可靠的配置和配置回读，特别是对于高密度FPGA。

公开(公告)号：US06961741B2

公开(公告)日：2005-11-01

申请号：US10076116

申请日：2002-02-14

Applicant: Parvesh Swami

Inventor： Parvesh Swami

IPC: G06F1/035 ,  G06F7/50 ,  G06F7/501 ,  H03K19/177 ,  G06F7/38

CPC classification number: G06F7/501 ,  G06F1/0356 ,  H03K19/17728

Abstract: A look-up table apparatus is provided for performing two-bit arithmetic operation including carry generation. The look-up table is modified to perform two concurrent combinatorial functions, or one function for an increased number of inputs. The look-up table can implement two full adders or subtractors, or two-bit counters, for example. One portion of the modified look-up table provides two bits of a sum output, and another portion of the modified table provides a fast carry out signal for application to a next stage of an adder/subtractor/counter.

Abstract translation: 提供了一种用于执行包括进位产生的两比特算术运算的查找表装置。 查找表被修改为执行两个并发组合函数，或者一个增加数量的输入的函数。 查找表可以实现两个完整的加法器或减法器，例如两位计数器。 经修改的查找表的一部分提供了和输出的两个比特，并且修改的表的另一部分提供了一个快速进位信号，用于应用于加法器/减法器/计数器的下一个级。

公开(公告)号：US20050035782A1

公开(公告)日：2005-02-17

申请号：US10830854

申请日：2004-04-23

Applicant: Parvesh Swami

Inventor： Parvesh Swami

IPC: H03K19/00 ,  H03K19/177 ,  H03K19/173

CPC classification number: H03K19/17772 ,  H03K19/0016 ,  H03K19/17784

Abstract: The present invention provides a programmable logic device with reduced power consumption comprising, a first set of data storage elements, at least a first power supply connected to the said first set of data storage elements, a second set of substantially identical interconnected tiles, each including logic blocks, at least a second power supply independent of the said first power supply connected to said identical tiles wherein said second power supply is switched-off when the logic block is not being used.

Abstract translation: 本发明提供了一种具有降低功耗的可编程逻辑器件，包括第一组数据存储元件，至少连接到所述第一组数据存储元件的第一电源，第二组基本相同的互连瓦片，每个包括 逻辑块，至少第二电源，独立于连接到所述相同瓦片的所述第一电源，其中当逻辑块未被使用时，所述第二电源被切断。

公开(公告)号：US07856467B2

公开(公告)日：2010-12-21

申请号：US11324019

申请日：2005-12-29

Applicant: Parvesh Swami ,  Ankur Bal

Inventor： Parvesh Swami ,  Ankur Bal

IPC: G06F7/52

CPC classification number: G06F7/523 ,  G06F7/5312

Abstract: The present invention provides an integrated circuit including at least one configurable logic cell capable of multiplication comprising an addition means for adding a first input and a partial product; a first multiplexing means for receiving a first output of said addition means at its first input and said partial product at its second input with its select line being controlled by second input, said first multiplexing means providing a first output; and a second multiplexing means for receiving a second output of said addition means at its first input and said second input at its second input with its select line being coupled to said second input, said second multiplexing means providing a second output.

Abstract translation: 本发明提供了一种集成电路，其包括能够进行乘法的至少一个可配置逻辑单元，该逻辑单元包括用于添加第一输入和部分乘积的加法装置; 第一多路复用装置，用于在其第一输入处接收所述加法装置的第一输出，在其第二输入处接收所述部分乘积，其选择线由第二输入控制，所述第一多路复用装置提供第一输出; 以及第二多路复用装置，用于在其第一输入处接收所述加法装置的第二输出，在其第二输入处接收所述第二输入，其选择线耦合到所述第二输入，所述第二多路复用装置提供第二输出。

公开(公告)号：US07154299B2

公开(公告)日：2006-12-26

申请号：US10407802

申请日：2003-04-04

Applicant: Parvesh Swami ,  Namerita Khanna ,  Deepak Agarwal

Inventor： Parvesh Swami ,  Namerita Khanna ,  Deepak Agarwal

IPC: H03K19/177

CPC classification number: H03K19/17736

Abstract: An improved Programmable Logic Device architecture that provides more efficient utilization of resources by enabling access to defined circuit elements in the domain of any Programmable Logic Block (PLB) from any other PLB in the device, by incorporating a connecting means in the routing structure for selectively connecting the input or output of the circuit element in the domain of the PLB to the common interconnect matrix connecting all the PLBs together.

公开(公告)号：US20060195503A1

公开(公告)日：2006-08-31

申请号：US11324019

申请日：2005-12-28

Applicant: Parvesh Swami ,  Ankur Bal

Inventor： Parvesh Swami ,  Ankur Bal

IPC: G06F7/52

CPC classification number: G06F7/523 ,  G06F7/5312

Abstract: The present invention provides an integrated circuit including at least one configurable logic cell capable of multiplication comprising an addition means for adding a first input and a partial product; a first multiplexing means for receiving a first output of said addition means at its first input and said partial product at its second input with its select line being controlled by second input, said first multiplexing means providing a first output; and a second multiplexing means for receiving a second output of said addition means at its first input and said second input at its second input with its select line being coupled to said second input, said second multiplexing means providing a second output.

Abstract translation: 本发明提供了一种集成电路，其包括能够进行乘法的至少一个可配置逻辑单元，该逻辑单元包括用于添加第一输入和部分乘积的加法装置; 第一多路复用装置，用于在其第一输入处接收所述加法装置的第一输出，在其第二输入处接收所述部分乘积，其选择线由第二输入控制，所述第一多路复用装置提供第一输出; 以及第二多路复用装置，用于在其第一输入处接收所述加法装置的第二输出，在其第二输入处接收所述第二输入，其选择线耦合到所述第二输入，所述第二多路复用装置提供第二输出。

公开(公告)号：US06864712B2

公开(公告)日：2005-03-08

申请号：US10426248

申请日：2003-04-28

Applicant: Deepak Agarwal ,  Parvesh Swami

Inventor： Deepak Agarwal ,  Parvesh Swami

IPC: G11C11/412 ,  H03K19/177

CPC classification number: G11C11/4125 ,  H03K19/17704 ,  H03K19/17764

Abstract: The present invention is concerned with a method and apparatus for hardening logic devices. The logic device has a plurality of memory cells forming an array connected by data lines and clock lines, and the device having a further connecting line. The method comprising: receiving data on said data lines for configuring each of the memory cells. Storing data in each of the memory cells by enabling at least one of the clock lines and when the desired data has been stored, hardening the array to fix the data by selectively connecting the data and clock lines to the further line.

Abstract translation: 本发明涉及用于硬化逻辑器件的方法和装置。 逻辑装置具有形成由数据线和时钟线连接的阵列的多个存储单元，并且该装置具有另外的连接线。 该方法包括：在所述数据线上接收用于配置每个存储单元的数据。 通过启用至少一个时钟线并且当期望的数据已经被存储时，通过使数据和时钟线选择性地连接到另一行，来硬化阵列以固定数据，将数据存储在每个存储器单元中。

公开(公告)号：US07196942B2

公开(公告)日：2007-03-27

申请号：US11254558

申请日：2005-10-20

Applicant: Anoop Khurana ,  Parvesh Swami

Inventor： Anoop Khurana ,  Parvesh Swami

IPC: G11C7/10 ,  G11C7/00

CPC classification number: G11C7/1051 ,  G11C7/106 ,  G11C7/1078 ,  G11C7/1087 ,  G11C11/419 ,  H03K19/1776 ,  H03K19/17776 ,  H03K19/17792

Abstract: A configuration memory structure includes one or more distributed buffers cascaded together, the output of a first buffer driving an output data line and complementary output data line which terminate at the input of a succeeding buffer. The first buffer includes precharging elements connected between a source and the data line and complementary data line, respectively; data sensing and holding elements connected between respective input and complementary input data lines and the data line and complementary data line, respectively; and tristate elements connected to the outputs of the data sensing and holding elements. This scheme provides fast and reliable configuration and configuration read back, especially for a high density FPGA.

Abstract translation: 配置存储器结构包括级联在一起的一个或多个分布式缓冲器，驱动输出数据线的第一缓冲器的输出和终止于后续缓冲器的输入端的互补输出数据线。 第一缓冲器包括分别连接在源与数据线和互补数据线之间的预充电元件; 数据传感和保持元件分别连接在相应的输入和互补输入数据线以及数据线和互补数据线之间; 并连接到数据传感和保持元件的输出的三态元件。 该方案提供快速可靠的配置和配置回读，特别是对于高密度FPGA。

公开(公告)号：US07167404B2

公开(公告)日：2007-01-23

申请号：US10436895

申请日：2003-05-13

Applicant: Shalini Pathak ,  Parvesh Swami

Inventor： Shalini Pathak ,  Parvesh Swami

IPC: G11C7/00

CPC classification number: G11C29/025 ,  G01R31/318516 ,  G11C29/02 ,  G11C29/12

Abstract: A programmable logic device (PLD) has the ability to test the configuration memory either independently or during configuration. The PLD may include a selector for selecting a particular column or row of the configuration memory array, and an input data storage device for storing configuration data required to be stored in the selected column or row, or test data for testing the selected column or row. The PLD may also include an output data storage device for storing the output from the selected column or row, and test logic that provides control signals for verifying the correct operation of the data lines of the configuration memory array without disturbing the data stored in the memory array.

Abstract translation: 可编程逻辑器件（PLD）能够独立地或在配置期间测试配置存储器。 PLD可以包括用于选择配置存储器阵列的特定列或行的选择器，以及用于存储需要存储在所选列或行中的配置数据的输入数据存储装置，或用于测试所选列或行的测试数据 。 PLD还可以包括用于存储来自所选择的列或行的输出的输出数据存储装置以及提供用于验证配置存储器阵列的数据线的正确操作的控制信号而不干扰存储在存储器中的数据的测试逻辑 数组。