公开(公告)号：US20170105284A1

公开(公告)日：2017-04-13

申请号：US15128904

申请日：2015-03-18

Applicant: Photonics Electronics Technology Research Association

Inventor： Takeshi AKAGAWA ,  Kenichiro YASHIKI

IPC: H05K1/11 ,  G02B6/42 ,  G02B6/122 ,  H05K1/18 ,  H05K1/02

CPC classification number: H05K1/111 ,  G02B6/122 ,  G02B6/4232 ,  H01L23/49844 ,  H01L2224/16225 ,  H05K1/0219 ,  H05K1/0243 ,  H05K1/0245 ,  H05K1/0251 ,  H05K1/181 ,  H05K3/4688 ,  H05K2201/10121 ,  H05K2201/10734 ,  Y02P70/611

Abstract: A pad-array arrangement structure on a substrate for mounting an IC chip on the substrate, wherein a structure with which it is possible to maximally avoid an increase in the number of wiring layers on the substrate is obtained by devising the pad arrangement in an IC pad-array region.A embodiment of the present invention provides a pad-array structure on a substrate for mounting an IC chip on the substrate. The present invention is characterized in that: a plurality of ground pads arrayed equidistantly in a first row, and a plurality of signal pads arrayed equidistantly in a second row on the inside of and parallel to the first row, are provided on a first circumferential edge in the pad-array region; each of the signal pads passes between two adjacent ground pads in the first row and is connected to an external circuit on the substrate; and electrical signals are input to and output from the external circuit.