公开(公告)号：USRE45885E1

公开(公告)日：2016-02-09

申请号：US14260240

申请日：2014-04-23

Applicant: Plastic Logic Limited

Inventor： Paul A. Cain ,  Carl Hayton

IPC: H01L21/00 ,  H01L21/461 ,  H01L51/00 ,  B23K26/06 ,  B23K26/40 ,  H05K3/02 ,  H01L21/268 ,  H01L21/768 ,  H05K3/46

CPC classification number: H01L51/0023 ,  B23K26/063 ,  B23K26/4075 ,  B23K2101/40 ,  B23K2103/16 ,  H01L21/268 ,  H01L21/76838 ,  H05K3/027 ,  H05K3/4644 ,  H05K2201/09672

Abstract: A method of fabricating an electronic device, the device including a plurality of layers on a substrate, the layers including an upper conductive layer and at least one patterned underlying layer between said conductive layer and said substrate. The method includes patterning said underlying layer, and patterning said upper conductive layer by laser ablation using a stepwise process in which successive areas of said upper conductive layer are ablated by successively applied laser patterns. The successively applied laser patterns overlap one another in an overlap region. The method further includes configuring a said laser pattern and said patterned underlying layer with respect to one another such that in a said overlap region said patterned underlying layer is substantially undamaged by said stepwise laser ablation.

Abstract translation: 一种制造电子器件的方法，所述器件在衬底上包括多个层，所述层包括上导电层和在所述导电层和所述衬底之间的至少一个图案化底层。 该方法包括图案化所述下层，以及通过使用逐步过程的激光烧蚀来图案化所述上导电层，其中所述上导电层的连续区域被依次施加的激光图案消融。 连续施加的激光图案在重叠区域中彼此重叠。 该方法还包括相对于彼此配置所述激光图案和所述图案化的下层，使得在所述重叠区域中，所述图案化下层通过所述逐步激光烧蚀基本上未损坏。