公开(公告)号：US11670622B2

公开(公告)日：2023-06-06

申请号：US17210452

申请日：2021-03-23

Applicant: Powertech Technology Inc.

Inventor： Yin-Huang Kung ,  Chia-Hung Lin ,  Fu-Yuan Yao ,  Chun-Wu Liu

IPC: H01L25/065 ,  H01L25/00

CPC classification number: H01L25/0657 ,  H01L25/50 ,  H01L2225/0651 ,  H01L2225/06575 ,  H01L2225/06586

Abstract: A stacked semiconductor package has a substrate, a first chip, at least one spacer, a second chip and an encapsulation. The first chip and the second chip are intersecting stacked on the substrate. The at least one spacer is stacked on the substrate to support the second chip. The encapsulation is formed to encapsulate the substrate, the first chip, the at least one spacer and the second chip. The at least one spacer is made of the material of the encapsulation. Therefore, the adhesion between the at least one spacer and the encapsulation is enhanced to avoid the delamination during the reliability test and enhances the reliability of the stacked semiconductor package.