公开(公告)号：US20220102232A1

公开(公告)日：2022-03-31

申请号：US17318066

申请日：2021-05-12

Applicant: Powertech Technology Inc.

Inventor： Shun-Ming YU ,  Han-Ming CHU

IPC: H01L23/31 ,  H01L21/56

Abstract: A semiconductor packaging structure includes a substrate, a wiring layer, a mask layer, and a sealing layer. The substrate has an effective region and a dummy region surrounding the effective region. The wiring layer is disposed on the effective and dummy regions, and is formed with a predetermined pattern including spaced-apart protrusions to define at least one cavity partially exposing the dummy region. The mask layer covers the wiring layer, and is formed with a through hole to communicate in space with the cavity. The through hole is smaller in size than the cavity, and cooperates with the cavity to form an accommodating space. The sealing layer covers the mask layer, and includes an engaging element filling the accommodating space and adhering to the substrate.