TEST HEAD ASSEMBLY FOR SEMICONDUCTOR DEVICE

    公开(公告)号:US20220334168A1

    公开(公告)日:2022-10-20

    申请号:US17467045

    申请日:2021-09-03

    Abstract: A test head assembly for a semiconductor device has a carrier, a pin seat and a test wire assembly. The carrier is formed in an L shape and has a lateral board, a perpendicular board and a opening formed through the perpendicular board. The pin seat is mounted in the corresponding opening. The test wire assembly has a teat head, a plurality of connectors and a plurality of test wires. The test head is mounted on an outer sidewall of the lateral board and connected to the pin seat through the test wires and the connectors. Therefore, the pin seat is mounted on the perpendicular board of the L-shaped uprightly and the test head is mounted on the lateral board. The pin seat and the test head are not parallel to each other, and a lateral size of the test head assembly is reduced to increase the space usage.

    DEVICE FOR OVER-THE-AIR TESTING
    2.
    发明申请

    公开(公告)号:US20220128623A1

    公开(公告)日:2022-04-28

    申请号:US17224196

    申请日:2021-04-07

    Abstract: A device for Over-the-Air testing includes a carrier unit, an automatic positioning member and a housing unit. The automatic positioning member is adapted to convey an object under test to an electrical connection zone of the carrier. The housing unit includes a housing shell, a pressing plate and a receiver. The housing shell defines a testing space that has an open end where the pressing plate is disposed. The housing unit and the carrier unit are movable relative to each other. When the carrier unit abuts the housing unit, the object under test is exposed to the testing space and is pressed against the electrical connection zone by the pressing plate so that electromagnetic waves from the object under test are received by the receiver.

    HEAD OF A TAG DEVICE
    3.
    发明申请

    公开(公告)号:US20220002020A1

    公开(公告)日:2022-01-06

    申请号:US17071384

    申请日:2020-10-15

    Abstract: A head of a tag device having a body, at least one row of negative-pressure through holes and at least one row of positive-pressure through holes. The body has a first surface and a second surface. The rows of negative and positive-pressure through holes are formed through the first and second surfaces of the body and arranged along a long-axis direction. Two negative and positive-pressure through holes at both ends of the corresponding row of negative and positive-pressure through holes are respectively close to the short sides of the body. Therefore, an effective labeling area is distributed between two short sides. The head of the tag device of the present invention provides a stable labeling operation for different products where different components are mounted and increases units per hour (UPH).

    MANUAL LABELING DEVICE
    4.
    发明申请

    公开(公告)号:US20220097891A1

    公开(公告)日:2022-03-31

    申请号:US17217207

    申请日:2021-03-30

    Abstract: A manual labeling device is disclosed. The manual labeling device has a platform, a plurality of positioning elements and a pivoting device. The platform has a labeling area. The positioning elements are mounted on the platform and around the labeling area. The pivoting device is pivotally mounted on one side of the platform and has a pivot shaft and a pivot arm. The operator manually places one product in the labeling area of the platform and the product is fixed in the labeling area by the positioning elements. The operator only pivots the pivot arm and the pivot arm directly aligns with the labeling area. Therefore, it does not take times to align the tool and the labeling area before attaching the label and the label attaching task is simplified to increase the productivity and quality of labeling (units per hour; UPH).

    WAFER-LEVEL TESTING METHOD FOR SINGULATED 3D-STACKED CHIP CUBES
    5.
    发明申请
    WAFER-LEVEL TESTING METHOD FOR SINGULATED 3D-STACKED CHIP CUBES 有权
    用于复合3D堆叠芯片的水平测试方法

    公开(公告)号:US20150061718A1

    公开(公告)日:2015-03-05

    申请号:US14018697

    申请日:2013-09-05

    CPC classification number: G01R31/2886

    Abstract: Disclosed is a wafer level testing method for testing a plurality of singulated 3D-stacked chip cubes by utilizing adjustable wafer maps to adjust the pick-and-place positions of the cubes on a carrier wafer. The wafer maps have a plurality of probe-card activated regions each including a plurality of component-attaching regions. Two wafer-level testing steps are performed on the cubes disposed on the carrier wafer according to the wafer maps. By analyzing the electrical testing results of the trial-run wafer-level testing step from the original wafer map, some prone-to-overkill component-attaching regions are confirmed and to create a corrected wafer map which the prone-to-overkill component-attaching regions are excluded from probe-card activated regions. Then, according to the corrected wafer map, cubes are disposed on the carrier wafer without disposing in the prone-to-overkill component-attaching regions. Accordingly, the real-production wafer-level testing step can be run smoothly without unnecessary shut down of adjustment or repair leading to the maximum productivity without overkill issues.

    Abstract translation: 公开了一种晶片级测试方法,用于通过利用可调节的晶片图来调整载体晶片上立方体的拾取和放置位置来测试多个单独的3D堆叠芯片立方体。 晶片图具有多个探针卡激活区域,每个区域包括多个分量附着区域。 根据晶片图,在设置在载体晶片上的立方体上执行两个晶片级测试步骤。 通过从原始晶片图分析试运行晶片级测试步骤的电测试结果,确定了一些倾向于过度杀伤的部件附着区域,并且产生校正的晶片图,其中倾斜过零点成分 - 探针卡激活区域中排除附着区域。 然后,根据校正的晶片图,立方体被布置在载体晶片上,而不设置在倾斜过零点部件附着区域中。 因此,实际生产的晶片级测试步骤可以顺利地运行,而不必关闭调整或修理,导致最大的生产率而不会出现过度的问题。

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