公开(公告)号：US20170084513A1

公开(公告)日：2017-03-23

申请号：US15369802

申请日：2016-12-05

Applicant: Powertech Technology Inc.

Inventor： Shou-Chian Hsu ,  Hiroyuki Fujishima

IPC: H01L23/367 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/3675 ,  H01L21/4846 ,  H01L21/486 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/6836 ,  H01L23/3114 ,  H01L23/36 ,  H01L23/42 ,  H01L23/49816 ,  H01L24/02 ,  H01L24/12 ,  H01L24/19 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68345 ,  H01L2221/68372 ,  H01L2224/0233 ,  H01L2224/0236 ,  H01L2224/02381 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2924/3511

Abstract: A semiconductor package including an insulating layer, a chip, a thermal interface material, a heat-dissipating cover and a re-distribution layer is provided. The insulating layer has an accommodating opening. The chip is disposed in the accommodating opening. The chip has an active surface, a back surface opposite to the active surface and a side surface connected to the active surface and the back surface. The thermal interface material is filled in the accommodating opening for at least encapsulating the side surface of the chip and exposing the active surface. The re-distribution layer and the heat-dissipating cover are disposed on two side of the insulating layer respectively. The heat-dissipating cover is thermally coupled to the chip through the thermal interface material. The re-distribution layer directly covers the insulating layer, the active surface of the chip and the thermal interface material, and the re-distribution layer is electrically connected to the chip.

公开(公告)号：US09553036B1

公开(公告)日：2017-01-24

申请号：US14794834

申请日：2015-07-09

Applicant: Powertech Technology Inc.

Inventor： Shou-Chian Hsu ,  Hiroyuki Fujishima

IPC: H01L25/065 ,  H01L21/48 ,  H01L23/36 ,  H01L21/56 ,  H01L25/00

CPC classification number: H01L23/3675 ,  H01L21/4846 ,  H01L21/486 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/6836 ,  H01L23/3114 ,  H01L23/36 ,  H01L23/42 ,  H01L23/49816 ,  H01L24/02 ,  H01L24/12 ,  H01L24/19 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68345 ,  H01L2221/68372 ,  H01L2224/0233 ,  H01L2224/0236 ,  H01L2224/02381 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2924/3511

Abstract: A semiconductor package including an insulating layer, a chip, a thermal interface material, a heat-dissipating cover and a re-distribution layer is provided. The insulating layer has an accommodating opening. The chip is disposed in the accommodating opening. The chip has an active surface, a back surface opposite to the active surface and a side surface connected to the active surface and the back surface. The thermal interface material is filled in the accommodating opening for at least encapsulating the side surface of the chip and exposing the active surface. The re-distribution layer and the heat-dissipating cover are disposed on two side of the insulating layer respectively. The heat-dissipating cover is thermally coupled to the chip through the thermal interface material. The re-distribution layer covers the active surface of the chip and the thermal interface material, and the re-distribution layer is electrically connected to the chip.

Abstract translation: 提供了包括绝缘层，芯片，热界面材料，散热盖和再分布层的半导体封装。 绝缘层具有容纳开口。 芯片设置在容纳开口中。 芯片具有活性表面，与活性表面相反的后表面和连接到活性表面和后表面的侧表面。 热界面材料填充在容纳开口中，用于至少封装芯片的侧表面并暴露活性表面。 再分配层和散热盖分别设置在绝缘层的两侧。 散热盖通过热界面材料热耦合到芯片。 再分配层覆盖芯片的活性表面和热界面材料，并且再分配层电连接到芯片。

公开(公告)号：US20170011983A1

公开(公告)日：2017-01-12

申请号：US14794834

申请日：2015-07-09

Applicant: Powertech Technology Inc.

Inventor： Shou-Chian Hsu ,  Hiroyuki Fujishima

IPC: H01L23/36 ,  H01L21/56

CPC classification number: H01L23/3675 ,  H01L21/4846 ,  H01L21/486 ,  H01L21/565 ,  H01L21/568 ,  H01L21/6835 ,  H01L21/6836 ,  H01L23/3114 ,  H01L23/36 ,  H01L23/42 ,  H01L23/49816 ,  H01L24/02 ,  H01L24/12 ,  H01L24/19 ,  H01L24/97 ,  H01L25/0657 ,  H01L25/50 ,  H01L2221/68345 ,  H01L2221/68372 ,  H01L2224/0233 ,  H01L2224/0236 ,  H01L2224/02381 ,  H01L2224/04105 ,  H01L2224/12105 ,  H01L2224/13024 ,  H01L2224/32225 ,  H01L2224/32245 ,  H01L2224/73267 ,  H01L2224/92244 ,  H01L2924/3511

Abstract: A semiconductor package including an insulating layer, a chip, a thermal interface material, a heat-dissipating cover and a re-distribution layer is provided. The insulating layer has an accommodating opening. The chip is disposed in the accommodating opening. The chip has an active surface, a back surface opposite to the active surface and a side surface connected to the active surface and the back surface. The thermal interface material is filled in the accommodating opening for at least encapsulating the side surface of the chip and exposing the active surface. The re-distribution layer and the heat-dissipating cover are disposed on two side of the insulating layer respectively. The heat-dissipating cover is thermally coupled to the chip through the thermal interface material. The re-distribution layer covers the active surface of the chip and the thermal interface material, and the re-distribution layer is electrically connected to the chip.

Abstract translation: 提供了包括绝缘层，芯片，热界面材料，散热盖和再分布层的半导体封装。 绝缘层具有容纳开口。 芯片设置在容纳开口中。 芯片具有活性表面，与活性表面相反的后表面和连接到活性表面和后表面的侧表面。 热界面材料填充在容纳开口中，用于至少封装芯片的侧表面并暴露活性表面。 再分配层和散热盖分别设置在绝缘层的两侧。 散热盖通过热界面材料热耦合到芯片。 再分配层覆盖芯片的活性表面和热界面材料，并且再分配层电连接到芯片。

公开(公告)号：US09099364B1

公开(公告)日：2015-08-04

申请号：US14460876

申请日：2014-08-15

Applicant: POWERTECH TECHNOLOGY INC.

Inventor： Shou-Chian Hsu

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L24/14 ,  H01L23/3157 ,  H01L23/3192 ,  H01L24/03 ,  H01L24/05 ,  H01L24/06 ,  H01L24/11 ,  H01L24/13 ,  H01L2224/0345 ,  H01L2224/03452 ,  H01L2224/0361 ,  H01L2224/03622 ,  H01L2224/039 ,  H01L2224/0401 ,  H01L2224/05023 ,  H01L2224/05155 ,  H01L2224/05166 ,  H01L2224/05568 ,  H01L2224/05582 ,  H01L2224/05583 ,  H01L2224/05647 ,  H01L2224/0603 ,  H01L2224/06102 ,  H01L2224/1146 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13021 ,  H01L2224/13023 ,  H01L2224/13082 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/1403 ,  H01L2224/1411 ,  H01L2224/14163 ,  H01L2224/14164 ,  H01L2224/14517 ,  H01L2224/16145 ,  H01L2224/16237 ,  H01L2224/17517 ,  H01L2224/94 ,  H01L2225/06513 ,  H01L2924/00014 ,  H01L2224/03 ,  H01L2224/11 ,  H01L2924/01074 ,  H01L2924/014

Abstract: Disclosed is a MPS-C2 (Metal Post Soldering Chip Connection) semiconductor device having shorter supporting posts. Bonding pads are reentrant from a wafer-level packaging (WLP) layer formed on the active surface. A patterned UBM metal layer includes a plurality of UBM pads disposed on the bonding pads and at least a UBM island disposed on the WLP layer. The island area of the UBM island on the WLP layer is at least four times larger than the unit area of the UBM pads. A plurality of I/O pillars are one-to-one disposed on the UBM pads by plating and a plurality of supporting pillars are many-to-one disposed on the UBM island by one plating process. The unit footprint of the supporting pillars on the UBM island is smaller than the unit footprint of the I/O pillars on the UBM pads so as to compensate the height difference between the top jointing surfaces of the supporting pillars and the I/O pillars.

Abstract translation: 公开了具有较短支撑柱的MPS-C2（金属后焊接芯片连接）半导体器件。 接合焊盘从形成在有源表面上的晶片级封装（WLP）层可重入。 图案化的UBM金属层包括设置在接合焊盘上的多个UBM焊盘和设置在WLP层上的至少一个UBM岛。 WLB层上的UBM岛的岛区比UBM垫的单位面积至少大四倍。 多个I / O柱通过电镀设置在UBM焊盘上一一对应，并且通过一次电镀工艺将多个支撑柱一对一布置在UBM岛上。 UBM岛上的支撑柱的单位占地面积小于UBM垫上的I / O支柱的单位尺寸，以补偿支撑柱的顶部接合表面与I / O柱之间的高度差。

公开(公告)号：US09419033B2

公开(公告)日：2016-08-16

申请号：US14523149

申请日：2014-10-24

Applicant: POWERTECH TECHNOLOGY INC.

Inventor： Shou-Chian Hsu ,  Wei-Chun Chao

IPC: H01L27/146

CPC classification number: H01L27/14618 ,  H01L27/14636 ,  H01L2224/13 ,  H01L2924/16235

Abstract: Disclosed is a chip scale package of image sensor having a dam combination, comprising an image sensor chip, a dam combination, a transparent lid disposed on the dam combination, and a plurality of external terminals disposed on the backside of the chip. An image sensing area is formed on the active surface of the image sensor chip. A dam combination consists essentially of at least two dam parts and has an image sensing window. The peripheries of the image sensor window are formed by a pre-formed dam part and are adjacent to the image sensing area with horizontal spacing not greater than 200 μm. There is a combination interface between the two dam parts. The combination interface and the post-formed dam part are far away from the image sensing area than the pre-formed dam part to keep residues caused by the disposition of the pre-formed dam part to be away from the 200 μm exclusive region around the image sensing area.

Abstract translation: 公开了一种具有坝组合的图像传感器的芯片级封装，包括图像传感器芯片，坝组合，设置在坝组合上的透明盖，以及设置在芯片背面的多个外部端子。 在图像传感器芯片的有源表面上形成图像感测区域。 大坝组合基本上由至少两个坝部组成，并具有图像感测窗口。 图像传感器窗口的周边由预形成的坝部形成，并且与水平间隔不大于200μm的图像感测区域相邻。 两个坝体之间有一个组合界面。 组合界面和形成后的坝部分远离图像感测区域，而不是预先形成的坝体部分，以保持预先形成的坝体部分所造成的残留物远离200μm左右的专用区域 图像感测区域。