公开(公告)号：US20180019320A1

公开(公告)日：2018-01-18

申请号：US15694375

申请日：2017-09-01

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd. ,  PURDUE RESEARCH FOUNDATION

Inventor： Peide Ye ,  Zhiyuan Cheng ,  Yi Xuan ,  Yanqing Wu ,  Bunmi Adekore ,  James Fiorenza

IPC: H01L29/66 ,  H01L29/51 ,  H01L21/28 ,  H01L29/778 ,  H01L21/02

Abstract: Methods of forming structures that include InP-based materials, such as a transistor operating as an inversion-type, enhancement-mode device are disclosed. A dielectric layer may be deposited by ALD over a semiconductor layer including In and P. A channel layer may be formed above a buffer layer having a lattice constant similar to a lattice constant of InP, the buffer layer being formed over a substrate having a lattice constant different from a lattice constant of InP.

公开(公告)号：US10000384B2

公开(公告)日：2018-06-19

申请号：US13906057

申请日：2013-05-30

Applicant: Purdue Research Foundation

Inventor： Xianfan Xu ,  Dapeng Wei ,  Peide Ye

IPC: C01B31/04 ,  C01B32/184 ,  B82Y30/00 ,  B82Y40/00 ,  C30B29/18

CPC classification number: C01B32/184 ,  B82Y30/00 ,  B82Y40/00 ,  C30B29/18

Abstract: A method of forming single and few layer graphene on a quartz substrate in one embodiment includes providing a quartz substrate, melting a portion of the quartz substrate, diffusing a form of carbon into the melted portion to form a carbon and quartz mixture, and precipitating at least one graphene layer out of the carbon and quartz mixture.

公开(公告)号：US10541315B2

公开(公告)日：2020-01-21

申请号：US15694375

申请日：2017-09-01

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd. ,  PURDUE RESEARCH FOUNDATION

Inventor： Peide Ye ,  Zhiyuan Cheng ,  Yi Xuan ,  Yanqing Wu ,  Bunmi Adekore ,  James Fiorenza

IPC: H01L21/02 ,  H01L29/78 ,  H01L29/66 ,  H01L29/51 ,  H01L21/28 ,  H01L29/778

Abstract: Methods of forming structures that include InP-based materials, such as a transistor operating as an inversion-type, enhancement-mode device are disclosed. A dielectric layer may be deposited by ALD over a semiconductor layer including In and P. A channel layer may be formed above a buffer layer having a lattice constant similar to a lattice constant of InP, the buffer layer being formed over a substrate having a lattice constant different from a lattice constant of InP.

公开(公告)号：US09780190B2

公开(公告)日：2017-10-03

申请号：US13654531

申请日：2012-10-18

Applicant: Taiwan Semiconductor Manufacturing Company, Ltd. ,  Purdue Research Foundation

Inventor： Peide Ye ,  Zhiyuan Cheng ,  Yi Xuan ,  Yanqing Wu ,  Bunmi Adekore ,  James Fiorenza

IPC: H01L29/66 ,  H01L29/778 ,  H01L21/02 ,  H01L21/28 ,  H01L29/51

CPC classification number: H01L29/66522 ,  H01L21/02299 ,  H01L21/02301 ,  H01L21/02392 ,  H01L21/28264 ,  H01L29/517 ,  H01L29/66446 ,  H01L29/66462 ,  H01L29/778

Abstract: Methods of forming structures that include InP-based materials, such as a transistor operating as an inversion-type, enhancement-mode device. A dielectric layer may be deposited by ALD over a semiconductor layer including In and P. A channel layer may be formed above a buffer layer having a lattice constant similar to a lattice constant of InP, the buffer layer being formed over a substrate having a lattice constant different from a lattice constant of InP.

公开(公告)号：US20130323158A1

公开(公告)日：2013-12-05

申请号：US13906057

申请日：2013-05-30

Applicant: Purdue Research Foundation

Inventor： Xianfan Xu ,  Dapeng Wei ,  Peide Ye

IPC: C01B31/04 ,  C03C17/22

CPC classification number: C01B32/184 ,  B82Y30/00 ,  B82Y40/00 ,  C30B29/18

Abstract: A method of forming single and few layer graphene on a quartz substrate in one embodiment includes providing a quartz substrate, melting a portion of the quartz substrate, diffusing a form of carbon into the melted portion to form a carbon and quartz mixture, and precipitating at least one graphene layer out of the carbon and quartz mixture.

Abstract translation: 在一个实施例中，在石英衬底上形成单层和几层石墨烯的方法包括提供石英衬底，熔化石英衬底的一部分，将碳的形式扩散到熔融部分中以形成碳和石英混合物，并在 碳和石英混合物中至少有一个石墨烯层。

公开(公告)号：US20230178441A1

公开(公告)日：2023-06-08

申请号：US17643214

申请日：2021-12-08

Applicant: Purdue Research Foundation

Inventor： Peide Ye ,  Mengwei Si

IPC: H01L21/8238 ,  H01L21/02 ,  H01L21/324

CPC classification number: H01L21/823821 ,  H01L21/0228 ,  H01L21/02181 ,  H01L21/324 ,  H01L29/7869

Abstract: Atomic layer deposited (ALD) oxide semiconductors for integrated circuits are disclosed. In one aspect, an ALD process is used to form an oxide semiconductor channel formed from Indium Oxide (In2O3) on a transistor formed in a back end of line (BEOL) process. In further aspects, the thickness of the In2O3 is controlled to a desired thickness and annealed to reduce defects. Still further aspects of the present disclosure may use this process on a fin-based field-effect transistor (FinFET).