公开(公告)号：US20200020473A1

公开(公告)日：2020-01-16

申请号：US16035378

申请日：2018-07-13

Applicant: QUALCOMM Incorporated

Inventor： Changhan Hobie YUN ,  Mario Francisco VELEZ ,  Nosun PARK ,  Wei-Chuan CHEN ,  Niranjan Sunil MUDAKATTE ,  Xiaoju YU ,  Paragkumar Ajaybhai THADESAR ,  Jonghae KIM

IPC: H01F17/00 ,  H01L49/02 ,  H01L23/522 ,  H01L27/02

Abstract: Aspects of the present disclosure provide three-dimensional (3D) through-glass-via (TGV) inductors for use in electronic devices. In some embodiments, a first portion of a 3D TGV inductor may be formed in a first wafer and a second portion of a 3D TGV may be formed in a second wafer. The first portion and second portion may be bonded together in a bonded wafer device thereby forming a larger inductor occupying relatively little wafer space on the first and the second wafers.

公开(公告)号：US20180047660A1

公开(公告)日：2018-02-15

申请号：US15233906

申请日：2016-08-10

Applicant: QUALCOMM Incorporated

Inventor： Chengjie ZUO ,  Mario Francisco VELEZ ,  Changhan Hobie YUN ,  David Francis BERDY ,  Daeik Daniel KIM ,  Jonghae KIM

IPC: H01L23/498 ,  H01L21/48 ,  H01L23/15 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L23/49805 ,  H01L21/4846 ,  H01L21/56 ,  H01L23/145 ,  H01L23/15 ,  H01L23/3121 ,  H01L23/49811 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/645 ,  H01L24/02 ,  H05K1/0218 ,  H05K3/3436 ,  H05K2201/10719

Abstract: A device includes a passive-on-glass (POG) structure and an interface layer. The POG structure includes a passive component and at least one contact pad on a first surface of a glass substrate. The interface layer has a second surface on the first surface of the glass substrate such that the passive component and the at least one contact pad are located between the first surface of the glass substrate and the interface layer. The interface layer includes at least one land grid array (LGA) pad formed on a third surface of the interface layer, where the third surface of the interface layer is opposite the second surface of the interface layer. The interface layer also includes at least one via formed in the interface layer configured to electrically connect the at least one contact pad with the at least one LGA pad.

公开(公告)号：US20170372975A1

公开(公告)日：2017-12-28

申请号：US15191062

申请日：2016-06-23

Applicant: QUALCOMM Incorporated

Inventor： Daeik Daniel KIM ,  David Francis BERDY ,  Changhan Hobie YUN ,  Mario Francisco VELEZ ,  Chengjie ZUO ,  Jonghae KIM

IPC: H01L21/66 ,  H01L23/544 ,  H01L23/66

CPC classification number: H01L22/32 ,  H01L23/544 ,  H01L27/13 ,  H01L2223/5446 ,  H01L2223/54493 ,  H03H7/00 ,  H03H7/1766 ,  H03H7/1791 ,  H03H7/463 ,  H03H2001/0078 ,  H04B1/0057

Abstract: A radio frequency (RF) integrated circuit may include a die having passive components including at least one pair of capacitors covered by a first dielectric layer supported by the die. The RF integrated circuit may also include an inline pad structure coupled to the at least one pair of capacitors proximate an edge of the die. The inline pad structure may include a first portion and a second portion extending into a dicing street toward the edge of the die and covered by at least a second dielectric layer.

公开(公告)号：US20170338788A1

公开(公告)日：2017-11-23

申请号：US15161138

申请日：2016-05-20

Applicant: QUALCOMM Incorporated

Inventor： Changhan Hobie YUN ,  David Francis BERDY ,  Chengjie ZUO ,  Daeik Daniel KIM ,  Jonghae KIM ,  Mario Francisco VELEZ ,  Niranjan Sunil MUDAKATTE ,  Robert Paul MIKULKA

IPC: H03H7/01 ,  H05K3/18 ,  H05K3/00 ,  H05K1/11 ,  H03H1/00 ,  H05K1/03 ,  H05K1/02 ,  H05K3/40 ,  H05K1/16

CPC classification number: H03H7/1758 ,  H01F5/003 ,  H01F41/04 ,  H01F41/041 ,  H01P1/203 ,  H01P1/2135 ,  H01P5/12 ,  H03H1/00 ,  H03H7/0115 ,  H03H7/09 ,  H03H7/1766 ,  H03H7/1775 ,  H03H7/463 ,  H03H2001/0078 ,  H05K1/0237 ,  H05K1/0306 ,  H05K1/115 ,  H05K1/162 ,  H05K1/165 ,  H05K1/186 ,  H05K3/0026 ,  H05K3/18 ,  H05K3/4038

Abstract: The present disclosure provides circuits and methods for fabricating circuits. A circuit may include an insulator having a first surface, a second surface, a periphery, a first subset of circuit elements disposed on the first surface, a second subset of circuit elements disposed on the second surface, and at least one conductive sidewall disposed on the periphery, wherein the conductive sidewall electrically couples the first subset of circuit elements to the second subset of circuit elements.

公开(公告)号：US20170125512A1

公开(公告)日：2017-05-04

申请号：US15375137

申请日：2016-12-11

Applicant: QUALCOMM Incorporated

Inventor： Changhan Hobie YUN ,  Daeik Daniel KIM ,  Chengjie ZUO ,  Jonghae KIM ,  Mario Francisco VELEZ ,  Donald William KIDWELL JR ,  Jon Bradley LASITER ,  Kwan-Yu LAI ,  Jitae KIM ,  Ravindra Vaman SHENOY

IPC: H01L49/02

CPC classification number: H01L28/90 ,  H01G4/012 ,  H01G4/33 ,  H01L21/28282 ,  H01L21/486 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5223 ,  H01L27/0805 ,  H01L27/12 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided are space-efficient capacitors that have a higher quality factor than conventional designs and improve coupling of electrical energy from a through-glass via (TGV) to a dielectric. For example, provided is a TGV having a non-rectangular cross-section, where one end of the TGV is coupled to a first metal plate. A dielectric material is formed on the first metal plate. A second metal plate is formed on the dielectric material in a manner that overlaps at least a portion of the first metal plate to form at least one overlapped region of the dielectric material. At least a part of the perimeter of the overlapped region is non-planar. The overlapped region can be formed in a shape of a closed ring, in a plurality of portions of a ring shape, in substantially a quarter of a ring shape, and/or in substantially a half of a ring shape.

公开(公告)号：US20160020013A1

公开(公告)日：2016-01-21

申请号：US14335609

申请日：2014-07-18

Applicant: QUALCOMM Incorporated

Inventor： David Francis BERDY ,  Chengjie ZUO ,  Daeik Daniel KIM ,  Changhan Hobie YUN ,  Mario Francisco VELEZ ,  Robert Paul MIKULKA ,  Jonghae KIM

IPC: H01F27/28 ,  H01F41/04 ,  H01F27/29

CPC classification number: H01F41/041 ,  H01F17/0013 ,  H01F27/2804 ,  H01F27/29 ,  H01F2017/004 ,  H01L23/5227 ,  H01L28/10 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A three-dimensional (3D) orthogonal inductor pair is embedded in and supported by a substrate, and has a first inductor having a first coil that winds around a first winding axis and a second inductor having a second coil that winds around a second winding axis. The second winding axis is orthogonal to the first winding axis. The second winding axis intersects the first winding axis at an intersection point that is within the substrate.

公开(公告)号：US20150228712A1

公开(公告)日：2015-08-13

申请号：US14177072

申请日：2014-02-10

Applicant: QUALCOMM Incorporated

Inventor： Changhan Hobie YUN ,  Daeik Daniel KIM ,  Chengjie ZUO ,  Jonghae KIM ,  Mario Francisco VELEZ ,  Donald William KIDWELL ,  Jon Bradley LASITER ,  Kwan-Yu LAI ,  Jitae KIM ,  Ravindra Vaman SHENOY

IPC: H01L49/02 ,  H01L23/48

CPC classification number: H01L28/90 ,  H01G4/012 ,  H01G4/33 ,  H01L21/28282 ,  H01L21/486 ,  H01L21/76898 ,  H01L23/481 ,  H01L23/5223 ,  H01L27/0805 ,  H01L27/12 ,  H01L28/60 ,  H01L2924/0002 ,  H01L2924/00

Abstract: Provided are space-efficient capacitors that have a higher quality factor than conventional designs and improve coupling of electrical energy from a through-glass via (TGV) to a dielectric. For example, provided is a TGV having a non-rectangular cross-section, where one end of the TGV is coupled to a first metal plate. A dielectric material is formed on the first metal plate. A second metal plate is formed on the dielectric material in a manner that overlaps at least a portion of the first metal plate to form at least one overlapped region of the dielectric material. At least a part of the perimeter of the overlapped region is non-planar. The overlapped region can be formed in a shape of a closed ring, in a plurality of portions of a ring shape, in substantially a quarter of a ring shape, and/or in substantially a half of a ring shape.

Abstract translation: 提供的空间效率电容器具有比传统设计更高的品质因数，并且改善了从直通玻璃通孔（TGV）到电介质的电能的耦合。 例如，提供了具有非矩形横截面的TGV，其中TGV的一端耦合到第一金属板。 在第一金属板上形成电介质材料。 第二金属板以与第一金属板的至少一部分重叠以形成电介质材料的至少一个重叠区域的方式形成在电介质材料上。 重叠区域的周边的至少一部分是非平面的。 重叠区域可以形成为环形的多个部分中的大致四分之一环形的闭环形状和/或大致一半的环形形状。

公开(公告)号：US20190067221A1

公开(公告)日：2019-02-28

申请号：US15839831

申请日：2017-12-12

Applicant: QUALCOMM Incorporated

Inventor： Jon Bradley LASITER ,  Ravindra Vaman SHENOY ,  Donald William KIDWELL, JR. ,  Mohammad Ali TASSOUDJI ,  Vladimir APARIN ,  Seong Heon JEONG ,  Jeremy DUNWORTH ,  Alireza MOHAMMADIAN ,  Mario Francisco VELEZ ,  Chin-Kwan KIM

IPC: H01L23/66 ,  H01L23/00 ,  H01L23/498 ,  H01L23/552 ,  H01L23/31 ,  H01L21/50 ,  H01Q1/22 ,  H01Q1/24

Abstract: In conventional packaging strategies for mm wave applications, the size of the package is dictated by the antenna size, which is often much larger than the RFIC (radio frequency integrated circuit). Also, the operations are often limited to a single frequency which limits their utility. In addition, multiple addition build-up layers are required to provide the necessary separation between the antennas and ground layers. To address these issues, it is proposed to provide a device that includes an antenna package, an RFIC package, and an interconnect assembly between the antenna and the RFIC packages. The interconnect assembly may comprise a plurality of interconnects with high aspect ratios and configured to connect one or more antennas of the antenna package with an RFIC of the RFIC package. An air gap may be formed in between the antenna package and the RFIC package for performance improvement.

公开(公告)号：US20190067219A1

公开(公告)日：2019-02-28

申请号：US15686131

申请日：2017-08-24

Applicant: QUALCOMM Incorporated

Inventor： Jon Bradley LASITER ,  Ravindra Vaman SHENOY ,  Donald William KIDWELL, JR. ,  Mohammad TASSOUDJI ,  Mario Francisco VELEZ

IPC: H01L23/66 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00 ,  H01L25/10 ,  H01L21/48 ,  H01L21/56 ,  H01L25/00 ,  H01Q1/22

Abstract: An package and related methods are disclosed. The package may include an antenna, an insert made of low-loss material, and a mold, wherein the mold directly contacts and surrounds at least a portion of the insert, wherein the antenna is formed of conductive material disposed at least in part on a surface of the insert.

公开(公告)号：US20180083589A1

公开(公告)日：2018-03-22

申请号：US15273596

申请日：2016-09-22

Applicant: QUALCOMM Incorporated

Inventor： Changhan Hobie YUN ,  Chengjie ZUO ,  David Francis BERDY ,  Mario Francisco VELEZ ,  Niranjan Sunil MUDAKATTE ,  Jonghae KIM

IPC: H03H7/46 ,  H03H7/01 ,  H03H1/00 ,  H03H3/00

CPC classification number: H03H7/0115 ,  H03H7/463 ,  H03H2001/0078 ,  H03H2001/0085 ,  H03H2007/013

Abstract: The present disclosure provides circuits and methods for fabricating circuits. A circuit may include a first insulator, a second insulator, a first subset of circuit elements disposed on a bottom surface of the first insulator, a second subset of circuit elements disposed on a top surface of the second insulator, one or more conductive couplings disposed between the first subset of circuit elements and the second subset of circuit elements.