公开(公告)号：US20240204795A1

公开(公告)日：2024-06-20

申请号：US18068941

申请日：2022-12-20

Applicant: QUALCOMM Incorporated

Inventor： Ashok SWAMINATHAN ,  Nitz SAPUTRA ,  Negar RASHIDI ,  Shahin MEHDIZAD TALEIE ,  Chinmaya MISHRA ,  Dongwon SEO ,  Jong Hyeon PARK ,  Sang-June PARK

IPC: H03M1/66 ,  H03M1/82

CPC classification number: H03M1/665 ,  H03M1/82

Abstract: Methods and apparatus for sharing digital-to-analog (DAC) converters in a reconfigurable DAC circuit to support two or more transmit chains of a wireless transmitter configured for different radio access technologies (RATs) and/or different transmitter architectures. One example DAC circuit generally includes at least four DACs and a plurality of switches coupled to outputs of the at least four DACs such that the DAC circuit is configured as a multi-channel DAC circuit with at least four channels for a first set of one or more frequency bands and as an interleaved DAC circuit with at least two channels for a second set of one or more frequency bands different from the first set of frequency bands.

公开(公告)号：US20230299757A1

公开(公告)日：2023-09-21

申请号：US17654916

申请日：2022-03-15

Applicant: QUALCOMM Incorporated

Inventor： Negar RASHIDI ,  Nitz SAPUTRA ,  Ashok SWAMINATHAN

IPC: H03K5/05 ,  H03M1/82

CPC classification number: H03K5/05 ,  H03M1/82

Abstract: In certain aspects, a method for providing a first drive clock signal and a second drive clock signal to a first sub-digital-to-analog converter (sub-DAC) and a second sub-DAC includes receiving an input clock signal, and dividing the input clock signal to generate a first divided clock signal and a second divided clock signal. The method also includes gating the input clock signal using the first divided clock signal to generate the first drive clock signal, and inputting the first drive clock signal to a clock input of the first sub-DAC. The method further includes gating the input clock signal using the second divided clock signal to generate the second drive clock signal, and inputting the second drive clock signal to a clock input of the second sub-DAC.