公开(公告)号：US20240178819A1

公开(公告)日：2024-05-30

申请号：US18509481

申请日：2023-11-15

Applicant: Qatar Foundation for Education, Science and Community Development

Inventor： Bo Wang ,  Jens Schneider

IPC: H03H17/02 ,  H03K19/20

CPC classification number: H03H17/02 ,  H03K19/20

Abstract: Linear decimation filters for incremental delta-sigma analog to digital converters are provided with a data rate signal input; a digital signal input; a weight generator connected to the signal input to generate a weight signal via a weight signal output; an adder having a digital signal output, a first addition input connected to the weight signal output, and a second addition input connected to the digital signal output; and an AND-gate having a first input connected to the input data rate signal input and a second input connected to the digital signal input to produce a logical output that gates output from the digital signal output of the adder.