公开(公告)号：US20070070077A1

公开(公告)日：2007-03-29

申请号：US11234943

申请日：2005-09-26

Applicant: R-ming Hsu

Inventor： R-ming Hsu

IPC: G09G5/00

CPC classification number: G06T15/005

Abstract: The present provides an instruction removing mechanism and a method using the same. The instruction removing mechanism is capable of scanning a graphic program to determine whether there is any simple texture load instruction (texld instruction) in the program. The simple texld instructions will be transmitted directly to the texture unit and deleted from a texld instruction collector to prevent the pixel shader executing the simple texld instructions before the texture unit.

Abstract translation: 本发明提供一种指令移除机制及其使用方法。 指令移除机构能够扫描图形程序以确定程序中是否存在任何简单的纹理加载指令（texld指令）。 简单的texld指令将直接发送到纹理单元，并从texld指令收集器中删除，以防止像素着色器在纹理单元之前执行简单的texld指令。

公开(公告)号：US20100177096A1

公开(公告)日：2010-07-15

申请号：US12400127

申请日：2009-03-09

Applicant: R-ming Hsu

Inventor： R-ming Hsu

IPC: G06T15/50 ,  G06T15/00

CPC classification number: G06T15/005

Abstract: An instruction folding mechanism, a method for performing the instruction folding mechanism and a pixel processing system employing the instruction folding mechanism are described. The pixel processing system comprises an instruction folding mechanism and a pixel shader. The instruction folding mechanism folds a plurality of first instructions in a first program to generate a second program having at least one second instruction which is a combination of the first instructions. The pixel shader connected to the instruction folding mechanism fetches the second program to decode at least the second instruction having the combination of the first instructions to execute the second program. The instruction folding mechanism comprises an instruction scheduler, a folding rule checker, and an instruction combiner. The instruction scheduler connected to the folding rule checker is used to scan the first instructions according to static positions in order to schedule the first instructions in the first program. The folding rule checker checks the first instructions according to a folding rule whether the first instructions has data independency. The instruction combiner connected to the folding rule checker can combine the first instructions having the data independency to generate at least the second instruction.

Abstract translation: 描述了指令折叠机构，执行指令折叠机构的方法以及采用指令折叠机构的像素处理系统。 像素处理系统包括指令折叠机构和像素着色器。 指令折叠机构在第一程序中折叠多个第一指令以产生具有作为第一指令的组合的至少一个第二指令的第二程序。 连接到指令折叠机构的像素着色器取出第二程序，以至少解码具有第一指令的组合的第二指令以执行第二程序。 指令折叠机构包括指令调度器，折叠规则检查器和指令组合器。 连接到折叠规则检查器的指令调度器用于根据静态位置扫描第一指令，以便调度第一程序中的第一指令。 折叠规则检查器根据折叠规则检查第一条指令是否第一条指令具有数据独立性。 连接到折叠规则检查器的指令组合器可以组合具有数据独立性的第一指令以产生至少第二指令。

公开(公告)号：US20080084424A1

公开(公告)日：2008-04-10

申请号：US11539773

申请日：2006-10-09

Applicant: R-ming Hsu

Inventor： R-ming Hsu

IPC: G06T1/00

CPC classification number: G06T1/20 ,  G06T15/80

Abstract: An early retiring instruction mechanism, a method for performing the early retiring instruction mechanism and a pixel processing system employing the early retiring instruction mechanism applied to a graphic processor unit (GPU) are described. The pixel processing system comprises an early retiring instruction mechanism and a pixel shader. The early retiring instruction mechanism selectively retires a plurality of instructions in a first program in order to generate at least one early retiring instruction in a second program. The pixel shader is connected to the early retiring instruction mechanism. The pixel shader fetches the second program and decodes at least one early retiring instruction to execute the second program therein for processing a plurality of pixels. Then, the pixel shader checks whether the pixels in the process of the early retiring instruction generated from early retiring instruction mechanism are directly issued to leave the pixel shader in advance. The early retiring instruction is an explicit retiring instruction, a retiring flow-control instruction or an instruction having a retire bit.

Abstract translation: 描述了早期退休指令机制，用于执行提前退休指令机制的方法和应用于图形处理器单元（GPU）的早期退休指令机制的像素处理系统。 像素处理系统包括早期退休指令机制和像素着色器。 早期退休指令机制选择性地在第一程序中退出多个指令，以便在第二程序中产生至少一个提前退休指令。 像素着色器连接到早期退休指令机制。 像素着色器取出第二程序并解码至少一个早期退出指令以执行其中的第二程序来处理多个像素。 然后，像素着色器检查是否直接发出从早期退休指令机制产生的早期退休指令的处理中的像素，以提前离开像素着色器。 早期退休指令是明确的退休指令，退休流程控制指令或具有退休位的指令。

公开(公告)号：US20060288193A1

公开(公告)日：2006-12-21

申请号：US11143674

申请日：2005-06-03

Applicant: R-ming Hsu

Inventor： R-ming Hsu

IPC: G06F9/30

CPC classification number: G06F9/30145 ,  G06F9/3017 ,  G06F9/382 ,  G06F9/384 ,  G06F9/3851

Abstract: A register-collecting mechanism and method using the same for multi-threaded processors are described. The register-collecting mechanism includes an instruction scanner, a register mapping table, an instruction modifier and an indication reporter. The instruction scanner scans one or more first programs having a plurality of first instructions and decode each of the first instructions to extract a plurality of nominal register numbers from the first instructions. The register mapping table compares the nominal register numbers of the first instructions to determine whether to collect a plurality of physical register numbers in sequence of register numbers when at least one of the nominal register numbers is unmapped with respective physical register number previously stored within the register mapping table. The instruction modifier is able to correct the nominal register numbers to generate a second program having a plurality of second instructions which are composed of the sequential physical register numbers collected in the register mapping table.

Abstract translation: 描述了一种用于多线程处理器的寄存器收集机制和方法。 寄存器收集机构包括指令扫描器，寄存器映射表，指令修改器和指示报告器。 指令扫描器扫描具有多个第一指令的一个或多个第一程序，并解码每个第一指令以从第一指令中提取多个标称寄存器号。 寄存器映射表比较第一指令的标称寄存器号码，以便当至少一个标称寄存器号与未预先存储在寄存器中的相应物理寄存器号码未映射时，确定是否以寄存器编号的顺序收集多个物理寄存器号 映射表。 指令修改器能够校正标称寄存器编号以产生具有由在寄存器映射表中收集的顺序物理寄存器编号组成的多个第二指令的第二程序。

公开(公告)号：US07502029B2

公开(公告)日：2009-03-10

申请号：US11333479

申请日：2006-01-17

Applicant: R-ming Hsu

Inventor： R-ming Hsu

IPC: G06T1/00 ,  G06T15/00 ,  G06F15/00 ,  G06F9/00

CPC classification number: G06T15/005

Abstract: An instruction folding mechanism, a method for performing the instruction folding mechanism and a pixel processing system employing the instruction folding mechanism are described. The pixel processing system comprises an instruction folding mechanism and a pixel shader. The instruction folding mechanism folds a plurality of first instructions in a first program to generate a second program having at least one second instruction which is a combination of the first instructions. The pixel shader connected to the instruction folding mechanism fetches the second program to decode at least the second instruction having the combination of the first instructions to execute the second program. The instruction folding mechanism comprises an instruction scheduler, a folding rule checker, and an instruction combiner. The instruction scheduler connected to the folding rule checker is used to scan the first instructions according to static positions in order to schedule the first instructions in the first program. The folding rule checker checks the first instructions according to a folding rule whether the first instructions has data independency. The instruction combiner connected to the folding rule checker can combine the first instructions having the data independency to generate at least the second instruction.

Abstract translation: 描述了指令折叠机构，执行指令折叠机构的方法以及采用指令折叠机构的像素处理系统。 像素处理系统包括指令折叠机构和像素着色器。 指令折叠机构在第一程序中折叠多个第一指令以产生具有作为第一指令的组合的至少一个第二指令的第二程序。 连接到指令折叠机构的像素着色器取出第二程序，以至少解码具有第一指令的组合的第二指令以执行第二程序。 指令折叠机构包括指令调度器，折叠规则检查器和指令组合器。 连接到折叠规则检查器的指令调度器用于根据静态位置扫描第一指令，以便调度第一程序中的第一指令。 折叠规则检查器根据折叠规则检查第一条指令是否第一条指令具有数据独立性。 连接到折叠规则检查器的指令组合器可以组合具有数据独立性的第一指令以产生至少第二指令。

公开(公告)号：US20070165028A1

公开(公告)日：2007-07-19

申请号：US11333479

申请日：2006-01-17

Applicant: R-ming Hsu

Inventor： R-ming Hsu

IPC: G06T15/50

CPC classification number: G06T15/005

Abstract: An instruction folding mechanism, a method for performing the instruction folding mechanism and a pixel processing system employing the instruction folding mechanism are described. The pixel processing system comprises an instruction folding mechanism and a pixel shader. The instruction folding mechanism folds a plurality of first instructions in a first program to generate a second program having at least one second instruction which is a combination of the first instructions. The pixel shader connected to the instruction folding mechanism fetches the second program to decode at least the second instruction having the combination of the first instructions to execute the second program. The instruction folding mechanism comprises an instruction scheduler, a folding rule checker, and an instruction combiner. The instruction scheduler connected to the folding rule checker is used to scan the first instructions according to static positions in order to schedule the first instrictions in the first program. The folding rule checker checks the first instructions according to a folding rule whether the first instructions has data independency. The instruction combiner connected to the folding rule checker can combine the first instructions having the data independency to generate at least the second instruction.

Abstract translation: 描述了指令折叠机构，执行指令折叠机构的方法以及采用指令折叠机构的像素处理系统。 像素处理系统包括指令折叠机构和像素着色器。 指令折叠机构在第一程序中折叠多个第一指令以产生具有作为第一指令的组合的至少一个第二指令的第二程序。 连接到指令折叠机构的像素着色器取出第二程序，以至少解码具有第一指令的组合的第二指令以执行第二程序。 指令折叠机构包括指令调度器，折叠规则检查器和指令组合器。 连接到折叠规则检查器的指令调度器用于根据静态位置扫描第一指令，以便调度第一程序中的第一个限制。 折叠规则检查器根据折叠规则检查第一条指令是否第一条指令具有数据独立性。 连接到折叠规则检查器的指令组合器可以组合具有数据独立性的第一指令以产生至少第二指令。