公开(公告)号：US20250167788A1

公开(公告)日：2025-05-22

申请号：US18516084

申请日：2023-11-21

Applicant: RENESAS ELECTRONICS AMERICA INC.

Inventor： Dong-Young CHANG ,  Steven Ernest FINN ,  Dominic WingKin YIP

IPC: H03L7/08 ,  H03K3/017 ,  H03K5/00 ,  H03K5/01

Abstract: Systems and methods for calibrating a clock signal are described. A device can include a processer, a circuit and a system duty cycle control (DCC) circuit. The circuit can perform a first phase shift on a clock signal to generate a first phase-shifted signal. The circuit can perform a second phase shift on the clock signal to generate a second phase-shifted signal. The circuit can perform a fixed DCC on the first phase-shifted signal to generate a first voltage signal. The circuit can sweep the second phase-shifted signal at a range of duty cycles to generate a second voltage signal. The circuit can sample an output clock signal at a time where the first voltage signal and the second voltage signal overlaps. The processor can generate a digital code based on the output clock signal. The system DCC circuit can calibrate the clock signal using the digital code.