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公开(公告)号：US12015414B2
公开(公告)日：2024-06-18
申请号：US17961741
申请日：2022-10-07
Applicant: RENESAS ELECTRONICS AMERICA INC.
Inventor： Menno Tjeerd Spijker
CPC classification number: H03L7/07 , H03L7/1075 , H03L7/23 , H04L7/0337
Abstract: Semiconductor devices for synchronizing networks are described. A semiconductor device can include an analog phase-lock loop (APLL) configured to output a first signal. The semiconductor device can further include a first digital phase-lock loop (DPLL) configured to output a second signal. The semiconductor device can further include a second DPLL configured to output a third signal. A combination of the first signal and the second signal can be used to generate a first output clock signal. A difference resulting from a subtraction of the second signal from the third signal can be used to generate a second output clock signal.
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公开(公告)号：US20240120924A1
公开(公告)日：2024-04-11
申请号：US17961741
申请日：2022-10-07
Applicant: RENESAS ELECTRONICS AMERICA INC.
Inventor： Menno Tjeerd Spijker
CPC classification number: H03L7/07 , H03L7/1075 , H03L7/23 , H04L7/0337
Abstract: Semiconductor devices for synchronizing networks are described. A semiconductor device can include an analog phase-lock loop (APLL) configured to output a first signal. The semiconductor device can further include a first digital phase-lock loop (DPLL) configured to output a second signal. The semiconductor device can further include a second DPLL configured to output a third signal. A combination of the first signal and the second signal can be used to generate a first output clock signal. A difference resulting from a subtraction of the second signal from the third signal can be used to generate a second output clock signal.
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