公开(公告)号：US20150179623A1

公开(公告)日：2015-06-25

申请号：US14567876

申请日：2014-12-11

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Yoshihiro ONO ,  Shinji WATANABE ,  Tsuyoshi KIDA ,  Kentaro MORI ,  Kenji SAKATA ,  Yusuke YAMADA

IPC: H01L25/00 ,  H01L23/00 ,  H01L21/56

CPC classification number: H01L25/50 ,  H01L21/568 ,  H01L23/3128 ,  H01L23/3135 ,  H01L24/13 ,  H01L24/16 ,  H01L24/29 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L24/91 ,  H01L25/0657 ,  H01L25/18 ,  H01L2224/13082 ,  H01L2224/13111 ,  H01L2224/13147 ,  H01L2224/16145 ,  H01L2224/16227 ,  H01L2224/27334 ,  H01L2224/29015 ,  H01L2224/29036 ,  H01L2224/2919 ,  H01L2224/321 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73104 ,  H01L2224/73204 ,  H01L2224/743 ,  H01L2224/75252 ,  H01L2224/75303 ,  H01L2224/75318 ,  H01L2224/75745 ,  H01L2224/81191 ,  H01L2224/81193 ,  H01L2224/81815 ,  H01L2224/83005 ,  H01L2224/83203 ,  H01L2224/8385 ,  H01L2224/83862 ,  H01L2224/9211 ,  H01L2225/06513 ,  H01L2225/06517 ,  H01L2225/06541 ,  H01L2225/06565 ,  H01L2924/181 ,  H01L2924/18161 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/00012 ,  H01L2924/01047 ,  H01L2224/81 ,  H01L2224/83

Abstract: To provide a semiconductor device having improved reliability.A semiconductor chip is conveyed onto a chip mounting region of a wiring board by means of a bonding jig to electrically couple the semiconductor chip and the wiring board to each other. The bonding jig for mounting the semiconductor chip on the wiring board is equipped with a retention portion for adsorbing and retaining a logic chip, a pressing portion for pressing against the back surface of the semiconductor chip, and a sealing portion to be firmly attached to the peripheral edge portion of the back surface of the semiconductor chip. The surface of the sealing portion to be firmly attached to the back surface of the semiconductor chip is made of a resin.

Abstract translation: 提供具有提高的可靠性的半导体器件。 通过接合夹具将半导体芯片传送到布线板的芯片安装区域，以将半导体芯片和布线板彼此电耦合。 用于将半导体芯片安装在布线板上的接合夹具配备有用于吸附和保持逻辑芯片的保持部分，用于按压半导体芯片的背面的按压部分和牢固地附接到半导体芯片的密封部分 半导体芯片的背面的周边部分。 要牢固地连接到半导体芯片的背面的密封部分的表面由树脂制成。

公开(公告)号：US20150380345A1

公开(公告)日：2015-12-31

申请号：US14750009

申请日：2015-06-25

Applicant: Renesas Electronics Corporation

Inventor： Yoshihiro ONO ,  Nobuhiro KINOSHITA ,  Tsuyoshi KIDA ,  Jumpei KONNO ,  Kenji SAKATA ,  Kentaro MORI ,  Shinji BABA

IPC: H01L23/495 ,  H01L23/544

CPC classification number: H01L23/49568 ,  H01L22/32 ,  H01L23/3128 ,  H01L23/4951 ,  H01L23/4952 ,  H01L23/49558 ,  H01L23/49811 ,  H01L23/544 ,  H01L24/05 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/45 ,  H01L24/81 ,  H01L24/97 ,  H01L25/0657 ,  H01L2223/5442 ,  H01L2223/54426 ,  H01L2224/0345 ,  H01L2224/0361 ,  H01L2224/03912 ,  H01L2224/0392 ,  H01L2224/0401 ,  H01L2224/05022 ,  H01L2224/05166 ,  H01L2224/05572 ,  H01L2224/05583 ,  H01L2224/05624 ,  H01L2224/05666 ,  H01L2224/06153 ,  H01L2224/06155 ,  H01L2224/11462 ,  H01L2224/1147 ,  H01L2224/11849 ,  H01L2224/13022 ,  H01L2224/13027 ,  H01L2224/1308 ,  H01L2224/13083 ,  H01L2224/131 ,  H01L2224/13147 ,  H01L2224/13155 ,  H01L2224/16105 ,  H01L2224/16225 ,  H01L2224/16238 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48227 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/8113 ,  H01L2224/81191 ,  H01L2224/97 ,  H01L2225/0651 ,  H01L2225/06517 ,  H01L2225/06565 ,  H01L2924/00011 ,  H01L2924/15311 ,  H01L2924/15313 ,  H01L2924/181 ,  H01L2224/81 ,  H01L2224/83 ,  H01L2224/32245 ,  H01L2924/00012 ,  H01L2924/00 ,  H01L2924/00014 ,  H01L2924/014 ,  H01L2924/01074 ,  H01L2924/013 ,  H01L2924/01014 ,  H01L2924/01029 ,  H01L2924/01033 ,  H01L2224/45147

Abstract: The reliability of a semiconductor device is improved. A probe mark is formed on a probe region of a pad covered with a protective insulating film. And, a pillar-shaped electrode has a first portion formed on an opening region and a second portion that is extended over the probe region from the upper portion of the opening region. At this time, a center position of the opening region is shifted from a center position of the pillar-shaped electrode that is opposed to a bonding finger.

Abstract translation: 提高了半导体器件的可靠性。 在覆盖有保护绝缘膜的焊盘的探针区域上形成探针标记。 并且，柱状电极具有形成在开口区域上的第一部分和从开口区域的上部在探针区域上延伸的第二部分。 此时，开口区域的中心位置从与接合手指相对的柱状电极的中心位置偏移。

公开(公告)号：US20170047296A1

公开(公告)日：2017-02-16

申请号：US15304015

申请日：2014-04-14

Applicant: Renesas Electronics Corporation

Inventor： Shinji WATANABE ,  Tsuyoshi KIDA ,  Yoshihiro ONO ,  Kentaro MORI ,  Kenji SAKATA ,  Yusuke YAMADA

IPC: H01L23/00 ,  H01L23/31

CPC classification number: H01L23/562 ,  H01L23/31 ,  H01L23/3128 ,  H01L24/02 ,  H01L24/16 ,  H01L24/42 ,  H01L24/97 ,  H01L2224/16145 ,  H01L2224/16225 ,  H01L2924/00014 ,  H01L2924/1431 ,  H01L2924/1434 ,  H01L2924/15174 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00012 ,  H01L2224/45099

Abstract: In a semiconductor device according to an embodiment, a second semiconductor chip is mounted on a first rear surface of a first semiconductor chip. Also, the first rear surface of the first semiconductor chip includes a first region in which a plurality of first rear electrodes electrically connected to the second semiconductor chip via a protrusion electrode are formed and a second region which is located on a peripheral side relative to the first region and in which a first metal pattern is formed. In addition, a protrusion height of the first metal pattern with respect to the first rear surface is smaller than a protrusion height of each of the plurality of first rear electrodes with respect to the first rear surface.

Abstract translation: 在根据实施例的半导体器件中，第二半导体芯片安装在第一半导体芯片的第一后表面上。 此外，第一半导体芯片的第一后表面包括第一区域，其中形成经由突起电极电连接到第二半导体芯片的多个第一后部电极，并且第二区域位于相对于第二半导体芯片的外围侧 第一区域，并且其中形成第一金属图案。 此外，第一金属图案相对于第一后表面的突出高度小于多个第一后电极中的每一个相对于第一后表面的突出高度。

公开(公告)号：US20150171066A1

公开(公告)日：2015-06-18

申请号：US14574662

申请日：2014-12-18

Applicant: Renesas Electronics Corporation

Inventor： Shintaro YAMAMICHI ,  Atsushi NAKAMURA ,  Masayuki ITO ,  Naoto TAOKA ,  Kentaro MORI

IPC: H01L25/18 ,  H01L27/02 ,  H01L23/31 ,  H01L23/34 ,  H01L29/49 ,  H01L29/51

CPC classification number: H01L25/18 ,  H01L23/145 ,  H01L23/147 ,  H01L23/15 ,  H01L23/3128 ,  H01L23/3142 ,  H01L23/49816 ,  H01L23/49827 ,  H01L23/49833 ,  H01L23/49894 ,  H01L23/5226 ,  H01L23/5283 ,  H01L24/97 ,  H01L27/0207 ,  H01L29/4916 ,  H01L29/517 ,  H01L2224/02166 ,  H01L2224/05553 ,  H01L2224/16145 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/45139 ,  H01L2224/48227 ,  H01L2224/48465 ,  H01L2224/49171 ,  H01L2224/73204 ,  H01L2224/73265 ,  H01L2224/83192 ,  H01L2224/92247 ,  H01L2224/97 ,  H01L2924/15184 ,  H01L2924/15311 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2224/48091 ,  H01L2924/00012 ,  H01L2924/00011

Abstract: This invention is to improve performance of a semiconductor integrated circuit device. A semiconductor device has a peripheral circuit chip and a logic chip mounted over a wiring substrate. The wiring substrate and the peripheral circuit chip are electrically connected, and the peripheral circuit chip and the logic chip are electrically connected. The peripheral circuit chip includes a first peripheral circuit, a power supply controller, a temperature sensor and a first RAM. The logic chip includes a CPU, a second peripheral circuit and a second RAM. The first peripheral circuit and the first RAM are manufactured based on a first process rule. The CPU, the second peripheral circuit and the second RAM are manufactured based on a second process rule finer than the first process rule.

Abstract translation: 本发明是为了提高半导体集成电路器件的性能。 半导体器件具有安装在布线基板上的外围电路芯片和逻辑芯片。 布线基板和外围电路芯片电连接，并且外围电路芯片和逻辑芯片电连接。 外围电路芯片包括第一外围电路，电源控制器，温度传感器和第一RAM。 逻辑芯片包括CPU，第二外围电路和第二RAM。 第一外围电路和第一RAM基于第一处理规则制造。 基于比第一处理规则更精细的第二处理规则来制造CPU，第二外围电路和第二RAM。