公开(公告)号：US11726175B2

公开(公告)日：2023-08-15

申请号：US17033257

申请日：2020-09-25

Applicant: Raytheon Company

Inventor： Joseph T. DeMarco ,  Brendan W. Jacobs ,  Tyler S. Lacy ,  Garrick D. Gaines ,  Edward J. Romic ,  Richard E. Jones ,  Avery R. Davis ,  Anthony J. Bristow ,  Thomas B. Butler ,  Dusty L. Clark ,  Scott S. Thoesen

IPC: G01S7/40

CPC classification number: G01S7/4052 ,  G01S7/4082

Abstract: A method includes receiving radar parameters from a unit under test (UUT). The method also includes generating a simulated radar return for the UUT using at least one graphics processing unit (GPU), where the simulated radar return includes digital signals. The method further includes controlling a timing of output of the simulated radar return to the UUT using at least one field programmable gate array (FPGA) carrier. The method also includes converting the digital signals into analog signals using multiple digital-to-analog converters (DACs). In addition, the method includes transmitting the analog signals to the UUT.

公开(公告)号：US20220099798A1

公开(公告)日：2022-03-31

申请号：US17033257

申请日：2020-09-25

Applicant: Raytheon Company

Inventor： Joseph T. DeMarco ,  Brendan W. Jacobs ,  Tyler S. Lacy ,  Garrick D. Gaines ,  Edward J. Romic ,  Richard E. Jones ,  Avery R. Davis ,  Anthony J. Bristow ,  Thomas B. Butler ,  Dusty L. Clark ,  Scott S. Thoesen

IPC: G01S7/40

Abstract: A method includes receiving radar parameters from a unit under test (UUT). The method also includes generating a simulated radar return for the UUT using at least one graphics processing unit (GPU), where the simulated radar return includes digital signals. The method further includes controlling a timing of output of the simulated radar return to the UUT using at least one field programmable gate array (FPGA) carrier. The method also includes converting the digital signals into analog signals using multiple digital-to-analog converters (DACs). In addition, the method includes transmitting the analog signals to the UUT.