公开(公告)号：US10447154B2

公开(公告)日：2019-10-15

申请号：US16030800

申请日：2018-07-09

Applicant: Renesas Electronics America Inc.

Inventor： Bin Li ,  Mehul Shah ,  Minghua Li ,  Eric Solie

IPC: H02M3/07 ,  H02M3/157

Abstract: According to certain aspects, the present embodiments are based on an improved switched-capacitor (SC) converter topology that typically does not include an inductor. In particular, the topology includes a ladder SC circuit configured as a cap divider. The cap divider can be used to provide an unregulated output voltage Vout that is a certain fraction (e.g. 2) of input voltage Vin, such as Vin/2 (i.e., duty cycle≈50%). In some embodiments of a PWM control scheme for this topology, the PWM OFF pulse is free running, determined by the logic combination of timer and VOUT comparator. The PWM OFF pulse width is measured and used as the reference for a minimum PWM ON timer. The PWM ON pulse is therefore forced to be at least a minimum width that is proportional to the PWM OFF pulse. A UVOV protection window can be added to ignore the minimum PWM ON timer during a load transient.

公开(公告)号：US11243551B1

公开(公告)日：2022-02-08

申请号：US17031323

申请日：2020-09-24

Applicant: Renesas Electronics America Inc.

Inventor： Zhigang Liang ,  Qian Sun ,  Bin Li

IPC: G05F1/46

Abstract: Exemplary implementations include dynamically compensating a system voltage by determining an actual load current based on a sense voltage across a sense resistor and a resistance of the sense resistor, the sense resistor being operatively coupled to a system node, generating a gain current based on the actual load current and a predetermined load current, determining a gain voltage based on a system gain and the gain current, and generating a compensation voltage based on a predetermined system voltage at a system node, an actual system voltage at the system node, and the gain voltage. Exemplary implementations also include calibrating a dynamic voltage compensation device by applying a predetermined voltage to a system node operatively coupled to the system load, a sense resistor, and an internal system node, determining a test current based on a sense voltage across the sense resistor and a resistance of the sense resistor, determining a system resistance based on the predetermined voltage, the test current, and an internal system voltage at the internal system node, and setting a system gain based on the system resistance at a gain block device.