公开(公告)号：US20230012015A1

公开(公告)日：2023-01-12

申请号：US17527661

申请日：2021-11-16

Applicant: Renesas Electronics America Inc.

Inventor： Juan Qiao ,  Chenxiao Ren ,  Yue Wang

IPC: H02M1/00 ,  G11C11/4074 ,  H02M3/07

Abstract: In an embodiment, an apparatus is disclosed that includes a power management integrated circuit (PMIC). The PMIC includes a voltage regulator supplied by a first power source and configured to generate a first output and a charge pump supplied by a second power source and configured to generate a second output. A bias voltage output of the power management integrated circuit is generated based at least in part on the first output and the second output. The charge pump is configured to adjust the second output based at least in part on a comparison between the bias voltage output and a reference voltage.

公开(公告)号：US20240213873A1

公开(公告)日：2024-06-27

申请号：US18435134

申请日：2024-02-07

Applicant: Renesas Electronics America Inc.

Inventor： Juan Qiao ,  Chenxiao Ren ,  Yue Wang

IPC: H02M1/00 ,  G11C11/4074 ,  H02M3/07

CPC classification number: H02M1/0045 ,  G11C11/4074 ,  H02M3/07

Abstract: In an embodiment, an apparatus is disclosed that includes a power management integrated circuit (PMIC). The PMIC includes a voltage regulator supplied by a first power source and configured to generate a first output and a charge pump supplied by a second power source and configured to generate a second output. A bias voltage output of the power management integrated circuit is generated based at least in part on the first output and the second output. The charge pump is configured to adjust the second output based at least in part on a comparison between the bias voltage output and a reference voltage.

公开(公告)号：US11929663B2

公开(公告)日：2024-03-12

申请号：US17527661

申请日：2021-11-16

Applicant: Renesas Electronics America Inc.

Inventor： Juan Qiao ,  Chenxiao Ren ,  Yue Wang

IPC: G11C11/4074 ,  H02M1/00 ,  H02M3/07

CPC classification number: H02M1/0045 ,  G11C11/4074 ,  H02M3/07

Abstract: In an embodiment, an apparatus is disclosed that includes a power management integrated circuit (PMIC). The PMIC includes a voltage regulator supplied by a first power source and configured to generate a first output and a charge pump supplied by a second power source and configured to generate a second output. A bias voltage output of the power management integrated circuit is generated based at least in part on the first output and the second output. The charge pump is configured to adjust the second output based at least in part on a comparison between the bias voltage output and a reference voltage.

公开(公告)号：US11815978B2

公开(公告)日：2023-11-14

申请号：US17566779

申请日：2021-12-31

Applicant: Renesas Electronics America Inc.

Inventor： Shwetal Arvind Patel ,  Chenxiao Ren

IPC: G06F1/32 ,  G06F1/3234

CPC classification number: G06F1/3275

Abstract: An apparatus includes a plurality of registers and a host interface comprising a plurality of pins. One of the plurality of registers may be a power state entry register configured to control entry to a low power state. One of the plurality of pins may be an enable pin. The apparatus may be configured to enter the low power state in response to setting the power state entry register to a first value and providing the enable pin a signal with a first level. The apparatus may be configured to exit the low power state in response to providing the enable pin the signal with a second level. The apparatus may enter an idle state after exiting the low power state. The low power state may consume less power than the idle state. The enable pin is implemented as an input configured to control a status of a plurality of regulators.

公开(公告)号：US20220197366A1

公开(公告)日：2022-06-23

申请号：US17566779

申请日：2021-12-31

Applicant: Renesas Electronics America Inc.

Inventor： Shwetal Arvind Patel ,  Chenxiao Ren

IPC: G06F1/3234

Abstract: An apparatus includes a plurality of registers and a host interface comprising a plurality of pins. One of the plurality of registers may be a power state entry register configured to control entry to a low power state. One of the plurality of pins may be an enable pin. The apparatus may be configured to enter the low power state in response to setting the power state entry register to a first value and providing the enable pin a signal with a first level. The apparatus may be configured to exit the low power state in response to providing the enable pin the signal with a second level. The apparatus may enter an idle state after exiting the low power state. The low power state may consume less power than the idle state. The enable pin is implemented as an input configured to control a status of a plurality of regulators.