公开(公告)号：US11561572B2

公开(公告)日：2023-01-24

申请号：US17136579

申请日：2020-12-29

Applicant: Renesas Electronics America Inc.

Inventor： Leon Goldin ,  Greg Armstrong

IPC: G06F1/04 ,  G06F1/14 ,  G06F1/10

Abstract: Methods and system for clock alignment are described. In an example, a timing device can distribute a clock signal to a line card via a trace of a backplane. The timing device can further send a pulse to the line card at a first time via the trace. The timing device can further receive a return pulse from the line card at a second time via the trace. The timing device can determine a time difference between the first time and the second time. The time difference can indicate a propagation delay associated with the line card and the trace. The timing device can send the time difference to the line card. The line card can adjust a phase delay offset of the line card using the time difference.

公开(公告)号：US11108400B1

公开(公告)日：2021-08-31

申请号：US17015259

申请日：2020-09-09

Applicant: Renesas Electronics America, Inc.

Inventor： Greg Armstrong

IPC: H03L7/197 ,  H03L7/199

Abstract: An apparatus includes a plurality of monitoring circuits and a reset circuit. The monitoring circuits may each be configured to determine a status of one of a plurality of input signals, transmit one of the input signals to a PLL circuit and generate a loss signal in response to the status. The reset circuit may be configured to receive the loss signal and generate a reset signal in response to the loss signal. One of the input signals may be a primary input used by the PLL circuit. One of the input signals may be a secondary input that has been selected to replace the primary input. The reset signal may be configured to reset a feedback clock divider of the PLL circuit.