公开(公告)号：US20200266823A1

公开(公告)日：2020-08-20

申请号：US16280196

申请日：2019-02-20

Applicant: Renesas Electronics America Inc.

Inventor： Min CHU

IPC: H03L7/14 ,  H03L7/07 ,  H03L7/091 ,  H03L7/107 ,  H04J3/06

Abstract: A phase-locked loop (PLL) performs hitless switching from a first reference clock (ref1) to a second reference clock (ref2) by entering holdover mode (418), and aligning the feedback clock (fbclk) to the second reference clock while in holdover mode. The alignment is performed by adjusting a divisor input (D) for the multi-mode divider (128) that divides the output clock frequency (PLLout) to generate the feedback clock. Other features are also provided.