公开(公告)号：US20150194368A1

公开(公告)日：2015-07-09

申请号：US14659444

申请日：2015-03-16

Applicant: Renesas Electronics Corporation

Inventor： Akito SHIMIZU ,  Kenji Nishikawa ,  Sadayuki Moroi ,  Tomoo Imura

IPC: H01L23/495 ,  H01L21/56

CPC classification number: H01L23/49503 ,  H01L21/56 ,  H01L21/561 ,  H01L21/563 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/3142 ,  H01L23/4952 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49551 ,  H01L23/49568 ,  H01L23/49579 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/05554 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48465 ,  H01L2224/49109 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/78301 ,  H01L2224/97 ,  H01L2924/00012 ,  H01L2924/181 ,  H01L2924/18301 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A method for manufacturing a semiconductor device, includes: (a) preparing a lead frame that includes a die pad having a first plane and a second plane located on the opposite side of the first plane, and a plurality of leads arranged next to the die pad; (b) mounting a semiconductor chip having a surface, a plurality of electrodes formed over the surface, and a reverse side located on the opposite side of the surface over a chip mounting area of the first plane of the die pad; (c) electrically coupling parts of the electrodes of the semiconductor chip and the leads through a plurality of first wires and electrically coupling the other parts of the electrodes and the die pad through a second wire.

Abstract translation: 一种制造半导体器件的方法，包括：（a）制备引线框架，该引线框架包括具有第一平面的管芯焊盘和位于第一平面的相对侧上的第二平面，以及设置在模具旁边的多个引线 垫; （b）安装具有表面的半导体芯片，形成在所述表面上的多个电极以及位于所述芯片安装区的所述第一平面的芯片安装区域的所述表面相反侧的反面; （c）通过多个第一布线电连接半导体芯片的电极和引线的部分，并通过第二导线电耦合电极和芯片焊盘的其它部分。

公开(公告)号：US20140001620A1

公开(公告)日：2014-01-02

申请号：US13898410

申请日：2013-05-20

Applicant: Renesas Electronics Corporation

Inventor： Akito Shimizu ,  Kenji Nishikawa ,  Sadayuki Moroi ,  Tomoo Imura

IPC: H01L23/495 ,  H01L21/56

CPC classification number: H01L23/49503 ,  H01L21/56 ,  H01L21/561 ,  H01L21/563 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/3142 ,  H01L23/4952 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49551 ,  H01L23/49568 ,  H01L23/49579 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/05554 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48465 ,  H01L2224/49109 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/78301 ,  H01L2224/97 ,  H01L2924/00012 ,  H01L2924/181 ,  H01L2924/18301 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A method according to the invention has a bonding process of mounting a semiconductor chip on an upper surface of a die pad that has the upper surface whose area is larger than a reverse side of the semiconductor chip. It also has a sealed body formation process of sealing the semiconductor chip so that an undersurface opposite to the upper surface of the die pad may be exposed after the bonding process. Here, the upper surface of the die pad is arranged around an area over which the semiconductor chip is mounted, and has a hollow part arrangement area in which a groove or multiple holes are formed. Moreover, surface roughness of the upper surface is made coarser than surface roughness of the undersurface.

Abstract translation: 根据本发明的方法具有将半导体芯片安装在具有面积大于半导体芯片的反面的上表面的管芯焊盘的上表面上的接合工艺。 它还具有密封半导体芯片的密封体形成工艺，使得在接合工艺之后可以暴露与芯片焊盘的上表面相对的下表面。 这里，芯片焊盘的上表面配置在安装有半导体芯片的区域周围，并且具有形成有槽或多个孔的中空部配置区域。 此外，上表面的表面粗糙度比下表面的表面粗糙度粗糙。

公开(公告)号：US09293396B2

公开(公告)日：2016-03-22

申请号：US14659444

申请日：2015-03-16

Applicant: Renesas Electronics Corporation

Inventor： Akito Shimizu ,  Kenji Nishikawa ,  Sadayuki Moroi ,  Tomoo Imura

IPC: H01L21/44 ,  H01L23/495 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/49503 ,  H01L21/56 ,  H01L21/561 ,  H01L21/563 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/3142 ,  H01L23/4952 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49551 ,  H01L23/49568 ,  H01L23/49579 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/05554 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48465 ,  H01L2224/49109 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/78301 ,  H01L2224/97 ,  H01L2924/00012 ,  H01L2924/181 ,  H01L2924/18301 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A method for manufacturing a semiconductor device, includes: (a) preparing a lead frame that includes a die pad having a first plane and a second plane located on the opposite side of the first plane, and a plurality of leads arranged next to the die pad; (b) mounting a semiconductor chip having a surface, a plurality of electrodes formed over the surface, and a reverse side located on the opposite side of the surface over a chip mounting area of the first plane of the die pad; (c) electrically coupling parts of the electrodes of the semiconductor chip and the leads through a plurality of first wires and electrically coupling the other parts of the electrodes and the die pad through a second wire.

Abstract translation: 一种制造半导体器件的方法，包括：（a）制备引线框架，该引线框架包括具有第一平面的管芯焊盘和位于第一平面的相对侧上的第二平面，以及设置在模具旁边的多个引线 垫; （b）安装具有表面的半导体芯片，形成在所述表面上的多个电极以及位于所述芯片安装区的所述第一平面的芯片安装区域的所述表面相反侧的反面; （c）通过多个第一布线电连接半导体芯片的电极和引线的部分，并通过第二导线电耦合电极和芯片焊盘的其它部分。

公开(公告)号：US09257400B2

公开(公告)日：2016-02-09

申请号：US14487762

申请日：2014-09-16

Applicant: Renesas Electronics Corporation

Inventor： Shinichi Uchida ,  Kenji Nishikawa ,  Masato Kanno ,  Mika Yonezawa ,  Shunichi Kaeriyama ,  Toshinori Kiyohara

IPC: H01L23/48 ,  H01L23/52 ,  H01L29/40 ,  H01L23/00 ,  H01L23/495 ,  H01L23/522 ,  H01L29/06 ,  H01L23/31

CPC classification number: H01L23/49575 ,  H01L23/3107 ,  H01L23/3171 ,  H01L23/48 ,  H01L23/49503 ,  H01L23/49513 ,  H01L23/49551 ,  H01L23/5227 ,  H01L24/06 ,  H01L24/29 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/83 ,  H01L24/85 ,  H01L24/92 ,  H01L25/0657 ,  H01L28/10 ,  H01L29/0657 ,  H01L2224/05554 ,  H01L2224/06155 ,  H01L2224/06181 ,  H01L2224/27003 ,  H01L2224/27334 ,  H01L2224/29034 ,  H01L2224/29139 ,  H01L2224/2919 ,  H01L2224/32013 ,  H01L2224/32057 ,  H01L2224/32135 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48249 ,  H01L2224/49113 ,  H01L2224/49171 ,  H01L2224/73215 ,  H01L2224/743 ,  H01L2224/75745 ,  H01L2224/83141 ,  H01L2224/83191 ,  H01L2224/92247 ,  H01L2924/00014 ,  H01L2924/13091 ,  H01L2924/181 ,  H01L2924/00 ,  H01L2924/00012 ,  H01L2224/45015 ,  H01L2924/207

Abstract: A semiconductor device has a chip mounting part, a first semiconductor chip, and a second semiconductor chip. The first semiconductor chip is mounted over the chip mounting part in a direction in which its first principal plane faces the chip mounting part. A part of the second semiconductor chip is mounted over the chip mounting part in a direction in which its third principal plane faces the first semiconductor chip. The element mounting part has a notch part. A part of the second semiconductor chip overlaps the notch part. In a region of the third principal plane of the second semiconductor chip that overlaps the notch part, a second electrode pad is provided.

Abstract translation: 半导体器件具有芯片安装部分，第一半导体芯片和第二半导体芯片。 第一半导体芯片沿其第一主平面面向芯片安装部分的方向安装在芯片安装部分上。 第二半导体芯片的一部分在其第三主平面面向第一半导体芯片的方向上安装在芯片安装部分上。 元件安装部分具有凹口部分。 第二半导体芯片的一部分与切口部分重叠。 在与切口部重叠的第二半导体芯片的第三主平面的区域中，设置有第二电极焊盘。

公开(公告)号：US09029195B2

公开(公告)日：2015-05-12

申请号：US14268847

申请日：2014-05-02

Applicant: Renesas Electronics Corporation

Inventor： Kenji Nishikawa

IPC: H01L21/00 ,  H01L21/66 ,  H01L23/495 ,  H01L23/544 ,  H01L23/00

CPC classification number: H01L22/12 ,  H01L23/495 ,  H01L23/49503 ,  H01L23/49575 ,  H01L23/544 ,  H01L24/32 ,  H01L24/48 ,  H01L24/83 ,  H01L24/85 ,  H01L2223/54426 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/83121 ,  H01L2224/8385 ,  H01L2224/85 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/07802 ,  H01L2924/181 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: A method of manufacturing a semiconductor device includes mounting at least one of a first semiconductor chip and a second semiconductor chip over a die pad of a leadframe, and inspecting a mounting position of at least one of the first semiconductor chip and the second semiconductor chip, wherein the leadframe includes first mark formed to the die pad, for indicating a first mounting region for the first semiconductor chip, and second mark formed to the die pad, for indicating a second mounting region for the second semiconductor chip, the first mark is different from the second mark, in at least either one of size and geometry, wherein, in the inspecting a mounting position of at least one of the first semiconductor chip and the second semiconductor chip, a mounting position of the first semiconductor chip is inspected when the first semiconductor chip is mounted.

Abstract translation: 一种制造半导体器件的方法包括将第一半导体芯片和第二半导体芯片中的至少一个安装在引线框架的管芯焊盘上，并且检查第一半导体芯片和第二半导体芯片中的至少一个的安装位置， 其中所述引线框架包括形成到所述管芯焊盘的第一标记，用于指示所述第一半导体芯片的第一安装区域以及形成于所述管芯焊盘的第二标记，用于指示用于所述第二半导体芯片的第二安装区域，所述第一标记是不同的 从所述第二标记，至少在尺寸和几何形状之一中，其中，在检查所述第一半导体芯片和所述第二半导体芯片中的至少一个的安装位置时，检查所述第一半导体芯片的安装位置， 首先安装半导体芯片。

公开(公告)号：US20140242734A1

公开(公告)日：2014-08-28

申请号：US14268847

申请日：2014-05-02

Applicant: Renesas Electronics Corporation

Inventor： Kenji Nishikawa

IPC: H01L21/66 ,  H01L23/00

CPC classification number: H01L22/12 ,  H01L23/495 ,  H01L23/49503 ,  H01L23/49575 ,  H01L23/544 ,  H01L24/32 ,  H01L24/48 ,  H01L24/83 ,  H01L24/85 ,  H01L2223/54426 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/83121 ,  H01L2224/8385 ,  H01L2224/85 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/07802 ,  H01L2924/181 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: A method of manufacturing a semiconductor device includes mounting at least one of a first semiconductor chip and a second semiconductor chip over a die pad of a leadframe, and inspecting a mounting position of at least one of the first semiconductor chip and the second semiconductor chip, wherein the leadframe includes first mark formed to the die pad, for indicating a first mounting region for the first semiconductor chip, and second mark formed to the die pad, for indicating a second mounting region for the second semiconductor chip, the first mark is different from the second mark, in at least either one of size and geometry, wherein, in the inspecting a mounting position of at least one of the first semiconductor chip and the second semiconductor chip, a mounting position of the first semiconductor chip is inspected when the first semiconductor chip is mounted.

Abstract translation: 一种制造半导体器件的方法包括将第一半导体芯片和第二半导体芯片中的至少一个安装在引线框架的管芯焊盘上，并且检查第一半导体芯片和第二半导体芯片中的至少一个的安装位置， 其中所述引线框架包括形成到所述管芯焊盘的第一标记，用于指示所述第一半导体芯片的第一安装区域以及形成于所述管芯焊盘的第二标记，用于指示用于所述第二半导体芯片的第二安装区域，所述第一标记是不同的 从所述第二标记，至少在尺寸和几何形状之一中，其中，在检查所述第一半导体芯片和所述第二半导体芯片中的至少一个的安装位置时，检查所述第一半导体芯片的安装位置， 首先安装半导体芯片。

公开(公告)号：US08786112B2

公开(公告)日：2014-07-22

申请号：US13933498

申请日：2013-07-02

Applicant: Renesas Electronics Corporation

Inventor： Kenji Nishikawa

IPC: H01L23/544 ,  H01L21/00

CPC classification number: H01L22/12 ,  H01L23/495 ,  H01L23/49503 ,  H01L23/49575 ,  H01L23/544 ,  H01L24/32 ,  H01L24/48 ,  H01L24/83 ,  H01L24/85 ,  H01L2223/54426 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/83121 ,  H01L2224/8385 ,  H01L2224/85 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/07802 ,  H01L2924/181 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: A semiconductor device includes a die pad including a first surface and a second surface opposite to the first surface, a first chip arranged in a first area on the first surface, the first chip including a first side and a second side crossing to the first side, a second chip arranged in a second area on the first surface, the second chip including a third side and a fourth side crossing to the third side, a plurality of first marks formed on the first surface, the first marks including a third mark and a fourth mark, a plurality of second marks formed on the first surface, the second marks including a fifth mark and sixth mark. The semiconductor device also includes a wire and a resin encapsulating the first chip, the second chip, and the wire.

Abstract translation: 半导体器件包括：芯片焊盘，包括第一表面和与第一表面相对的第二表面;第一芯片，布置在第一表面上的第一区域中，第一芯片包括第一侧面和与第一侧面交叉的第二侧面 ，第二芯片，布置在所述第一表面上的第二区域中，所述第二芯片包括与所述第三侧交叉的第三侧和第四侧，形成在所述第一表面上的多个第一标记，所述第一标记包括第三标记和 第四标记，形成在第一表面上的多个第二标记，第二标记包括第五标记和第六标记。 该半导体器件还包括一个线和一个封装第一芯片，第二芯片和电线的树脂。

公开(公告)号：US09741641B2

公开(公告)日：2017-08-22

申请号：US14997509

申请日：2016-01-16

Applicant: Renesas Electronics Corporation

Inventor： Akito Shimizu ,  Kenji Nishikawa ,  Sadayuki Moroi ,  Tomoo Imura

IPC: H01L23/495 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/49503 ,  H01L21/56 ,  H01L21/561 ,  H01L21/563 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/3142 ,  H01L23/4952 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49551 ,  H01L23/49568 ,  H01L23/49579 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/05554 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48465 ,  H01L2224/49109 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/78301 ,  H01L2224/97 ,  H01L2924/00012 ,  H01L2924/181 ,  H01L2924/18301 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A semiconductor device, includes a die pad that has a first main surface and a second main surface located on the opposite side of the first main surface; a lead arranged next to the die pad; a semiconductor chip that has a surface, a first electrode and a second electrode formed on the surface, and a reverse side located on the opposite side of the surface, and is mounted on a chip mounting area of the first main of the die pad; a first wire that electrically couples the first electrode of the semiconductor chip and the lead; a second wire that electrically couples the second electrode of the semiconductor chip and the die pad; and a sealed body that seals the semiconductor chip, the first wire, and the second wire.

公开(公告)号：US09018745B2

公开(公告)日：2015-04-28

申请号：US13898410

申请日：2013-05-20

Applicant: Renesas Electronics Corporation

Inventor： Akito Shimizu ,  Kenji Nishikawa ,  Sadayuki Moroi ,  Tomoo Imura

IPC: H01L23/495 ,  H01L21/56 ,  H01L23/00 ,  H01L23/31

CPC classification number: H01L23/49503 ,  H01L21/56 ,  H01L21/561 ,  H01L21/563 ,  H01L23/3107 ,  H01L23/3114 ,  H01L23/3142 ,  H01L23/4952 ,  H01L23/49541 ,  H01L23/49548 ,  H01L23/49551 ,  H01L23/49568 ,  H01L23/49579 ,  H01L24/32 ,  H01L24/45 ,  H01L24/48 ,  H01L24/49 ,  H01L24/73 ,  H01L24/97 ,  H01L2224/05554 ,  H01L2224/32245 ,  H01L2224/45144 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/48257 ,  H01L2224/48465 ,  H01L2224/49109 ,  H01L2224/49171 ,  H01L2224/73265 ,  H01L2224/78301 ,  H01L2224/97 ,  H01L2924/00012 ,  H01L2924/181 ,  H01L2924/18301 ,  H01L2924/00014 ,  H01L2924/00

Abstract: A method according to the invention has a bonding process of mounting a semiconductor chip on an upper surface of a die pad that has the upper surface whose area is larger than a reverse side of the semiconductor chip. It also has a sealed body formation process of sealing the semiconductor chip so that an undersurface opposite to the upper surface of the die pad may be exposed after the bonding process. Here, the upper surface of the die pad is arranged around an area over which the semiconductor chip is mounted, and has a hollow part arrangement area in which a groove or multiple holes are formed. Moreover, surface roughness of the upper surface is made coarser than surface roughness of the undersurface.

Abstract translation: 根据本发明的方法具有将半导体芯片安装在具有面积大于半导体芯片的反面的上表面的管芯焊盘的上表面上的接合工艺。 它还具有密封半导体芯片的密封体形成工艺，使得在接合工艺之后可以暴露与芯片焊盘的上表面相对的下表面。 这里，芯片焊盘的上表面配置在安装有半导体芯片的区域周围，并且具有形成有槽或多个孔的中空部配置区域。 此外，上表面的表面粗糙度比下表面的表面粗糙度粗糙。

公开(公告)号：US20130285227A1

公开(公告)日：2013-10-31

申请号：US13933498

申请日：2013-07-02

Applicant: Renesas Electronics Corporation

Inventor： Kenji Nishikawa

IPC: H01L23/495

CPC classification number: H01L22/12 ,  H01L23/495 ,  H01L23/49503 ,  H01L23/49575 ,  H01L23/544 ,  H01L24/32 ,  H01L24/48 ,  H01L24/83 ,  H01L24/85 ,  H01L2223/54426 ,  H01L2224/32145 ,  H01L2224/48091 ,  H01L2224/48247 ,  H01L2224/83121 ,  H01L2224/8385 ,  H01L2224/85 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01033 ,  H01L2924/01082 ,  H01L2924/07802 ,  H01L2924/181 ,  H01L2224/45099 ,  H01L2224/05599 ,  H01L2924/00012

Abstract: A semiconductor device includes a die pad including a first surface and a second surface opposite to the first surface, a first chip arranged in a first area on the first surface, the first chip including a first side and a second side crossing to the first side, a second chip arranged in a second area on the first surface, the second chip including a third side and a fourth side crossing to the third side, a plurality of first marks formed on the first surface, the first marks including a third mark and a fourth mark, a plurality of second marks formed on the first surface, the second marks including a fifth mark and sixth mark. The semiconductor device also includes a wire and a resin encapsulating the first chip, the second chip, and the wire.

Abstract translation: 半导体器件包括：芯片焊盘，包括第一表面和与第一表面相对的第二表面;第一芯片，布置在第一表面上的第一区域中，第一芯片包括第一侧面和与第一侧面交叉的第二侧面 ，第二芯片，布置在所述第一表面上的第二区域中，所述第二芯片包括与所述第三侧交叉的第三侧和第四侧，形成在所述第一表面上的多个第一标记，所述第一标记包括第三标记和 第四标记，形成在第一表面上的多个第二标记，第二标记包括第五标记和第六标记。 该半导体器件还包括一个线和一个封装第一芯片，第二芯片和电线的树脂。