公开(公告)号：US10901152B2

公开(公告)日：2021-01-26

申请号：US15871504

申请日：2018-01-15

Applicant: Renesas Electronics Corporation

Inventor： Tatsuya Usami

IPC: G02B6/13 ,  G02B6/122 ,  G02F1/025 ,  G02F1/01 ,  G02B6/132 ,  G02B6/12 ,  G02B6/43 ,  H01L31/0232 ,  H01L31/18

Abstract: An SOI substrate is attracted to and detached from an electrostatic chuck included in a semiconductor manufacturing device without failures. A semiconductor device includes a semiconductor substrate made of silicon, a first insulating film formed on a main surface of the semiconductor substrate and configured to generate compression stress to silicon, a waveguide, made of silicon, formed on the first insulating film, and a first interlayer insulating film formed on the first insulating film so as to cover the waveguide. Further, a second insulating film configured to generate tensile stress to silicon is formed on the first interlayer insulating film and in a region distant from the optical waveguide by a thickness of the first insulating film or larger. The second insulating film offsets the compression of the first insulating film.

公开(公告)号：US10162110B2

公开(公告)日：2018-12-25

申请号：US15243718

申请日：2016-08-22

Applicant: Renesas Electronics Corporation ,  Photonics Electronics Technology Research Association

Inventor： Tatsuya Usami ,  Keiji Sakamoto ,  Yoshiaki Yamamoto ,  Shinichi Watanuki ,  Masaru Wakabayashi ,  Tohru Mogami ,  Tsuyoshi Horikawa ,  Keizo Kinoshita

IPC: G02B6/12 ,  G02B6/132 ,  G02B6/136

Abstract: A semiconductor device is provided with an insulating layer formed on a base substrate, an optical waveguide composed of a semiconductor layer formed on the insulating layer, and an insulating film formed along an upper surface of the insulating layer and a front surface of the optical waveguide. A peripheral edge portion of a lower surface of the optical waveguide is separated from the insulating layer, and the insulating film is buried between the peripheral edge portion and the insulating layer.

公开(公告)号：US10120129B2

公开(公告)日：2018-11-06

申请号：US15789655

申请日：2017-10-20

Applicant: Renesas Electronics Corporation

Inventor： Tatsuya Usami

IPC: G02B6/10 ,  G02B6/122 ,  G02B6/13 ,  G02F1/025 ,  G02B6/12

Abstract: Good optical properties can be achieved in an optical waveguide made of polycrystalline silicon.A semiconductor layer that constitutes each of a first optical signal line, a second optical signal line, a grating coupler, an optical modulator, and a p-type layer of a germanium optical receiver is formed by a polycrystalline silicon film. Crystal grains of polycrystalline silicon exposed on an upper surface of the semiconductor layer include crystal grains having flat surfaces parallel to a first main surface of a semiconductor substrate, and crystal grains of polycrystalline silicon exposed on side surfaces (including side surfaces of a protrusion of a protruding portion) of the semiconductor layer include crystal grains having flat surfaces perpendicular to the first main surface of the semiconductor substrate.

公开(公告)号：US20130249084A1

公开(公告)日：2013-09-26

申请号：US13767446

申请日：2013-02-14

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tatsuya Usami ,  Tomoyuki Nakamura ,  Naoki Fujimoto

IPC: H01L23/00

CPC classification number: H01L24/13 ,  H01L21/563 ,  H01L23/5329 ,  H01L23/53295 ,  H01L24/03 ,  H01L24/05 ,  H01L24/11 ,  H01L24/16 ,  H01L24/32 ,  H01L24/81 ,  H01L24/83 ,  H01L2224/0345 ,  H01L2224/0401 ,  H01L2224/05098 ,  H01L2224/05541 ,  H01L2224/05655 ,  H01L2224/1132 ,  H01L2224/1146 ,  H01L2224/11849 ,  H01L2224/13099 ,  H01L2224/13111 ,  H01L2224/16225 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/81191 ,  H01L2224/83104 ,  H01L2924/1306 ,  H01L2924/15311 ,  H01L2924/16152 ,  H01L2924/16251 ,  H01L2924/3512 ,  H01L2924/01047 ,  H01L2924/00014 ,  H01L2924/00 ,  H01L2924/00012

Abstract: A semiconductor device includes an interlayer insulating film containing Si, O, C, and H, an under-bump metal film disposed over the interlayer insulating film and containing Ni, and a bump electrode disposed over the under-bump metal film. In the interlayer insulating film, a ratio of a peak height of Si—CH3 near a wave number 1270 cm−1 to a peak height of Si—O near a wave number 1030 cm−1 obtained by Fourier-transform infrared spectroscopy (FTIR) is 0.15 or greater and 0.27 or less. A ratio of a peak height of Si—CH2—Si near a wave number 1360 cm−1 to the peak height of Si—CH3 near the wave number 1270 cm−1 is 0.031 or greater.

Abstract translation: 半导体器件包括含有Si，O，C和H的层间绝缘膜，设置在层间绝缘膜上并包含Ni的凸起下金属膜，以及设置在凸块下金属膜上的凸块电极。 在层间绝缘膜中，通过傅里叶变换红外光谱（FTIR）获得的波数1270cm -1附近的Si-CH 3的峰高与靠近波数1030cm -1的Si-O的峰高的比率， 为0.15以上且0.27以下。 波数1360cm -1附近的Si-CH 2 -Si的峰高与波数1270cm -1附近的Si-CH 3的峰高的比率为0.031以上。

公开(公告)号：US10714330B2

公开(公告)日：2020-07-14

申请号：US15934710

申请日：2018-03-23

Applicant: Renesas Electronics Corporation

Inventor： Tomoo Nakayama ,  Tatsuya Usami

IPC: H01L21/3205 ,  H01L29/76 ,  H01L29/94 ,  H01L21/02 ,  H01L29/66 ,  H01L21/3213 ,  H01L21/265 ,  H01L21/266 ,  H01L21/8238

Abstract: The reliability of a semiconductor device is improved. A photoresist pattern is formed over a semiconductor substrate. Then, over the semiconductor substrate, a protective film is formed in such a manner as to cover the photoresist pattern. Then, with the photoresist pattern covered with the protective film, an impurity is ion implanted into the semiconductor substrate. Thereafter, the protective film is removed by wet etching, and then, the photoresist pattern is removed.

公开(公告)号：US10295743B2

公开(公告)日：2019-05-21

申请号：US14827779

申请日：2015-08-17

Applicant: Renesas Electronics Corporation

Inventor： Hiroyuki Kunishima ,  Yasutaka Nakashiba ,  Masaru Wakabayashi ,  Shinichi Watanuki ,  Ken Ozawa ,  Tatsuya Usami ,  Yoshiaki Yamamoto ,  Keiji Sakamoto

IPC: G02B6/12 ,  G02B6/125 ,  G02B6/136

Abstract: Disclosed is an optical semiconductor device which can be improved in light shift precision and restrained from undergoing a loss in light transmission. In this device, an inner side-surface of a first optical coupling portion of an optical coupling region and an inner side-surface of a second optical coupling portion of the region are increased in line edge roughness. This manner makes light coupling ease from a first to second optical waveguide. By contrast, the following are decreased in line edge roughness: an outer side-surface of the first optical coupling portion of the optical coupling region; an outer side-surface of the second optical coupling portion of the region; two opposed side-surfaces of a portion of the first optical waveguide, the portion being any portion other than the region; and two opposed side-surfaces of a portion of the second optical waveguide, the portion being any portion other than the region.

公开(公告)号：US10256135B2

公开(公告)日：2019-04-09

申请号：US15786366

申请日：2017-10-17

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tatsuya Usami

IPC: H01L21/76 ,  H01L21/768 ,  H01L21/762 ,  H01L21/764 ,  H01L21/8234 ,  H01L21/8238 ,  H01L27/092 ,  H01L21/74 ,  H01L29/06 ,  H01L21/285

Abstract: To provide a semiconductor device having a substrate contact in a deep trench thereof and having an improved characteristic. A PVD-metal film (metal film formed by PVD) is used as a first barrier metal film which is a lowermost layer barrier metal film formed in a deep trench penetrating an n type epitaxial layer and a reaching a layer therebelow. Such a configuration makes it possible to stably form a metal silicide layer at a boundary between the PVD-metal film and a silicon layer therebelow (or silicon substrate) and thereby stabilize the contact resistance.

公开(公告)号：US09559175B2

公开(公告)日：2017-01-31

申请号：US14714958

申请日：2015-05-18

Applicant: Renesas Electronics Corporation

Inventor： Tatsuya Usami

IPC: H01L29/66 ,  H01L29/417 ,  H01L29/78

CPC classification number: H01L29/41775 ,  H01L21/7682 ,  H01L21/76885 ,  H01L23/485 ,  H01L23/5222 ,  H01L23/53295 ,  H01L29/41783 ,  H01L29/665 ,  H01L29/6656 ,  H01L29/6659 ,  H01L29/66628 ,  H01L29/66636 ,  H01L29/7833 ,  H01L29/7834

Abstract: The parasitic capacitance formed by a gate electrode, a contact, and a side wall is reduced.The gate electrode and the side wall are covered by an insulating layer. The contact passes through the insulating layer and is connected to a diffusion layer. Then, an air gap is located between the side wall and the contact. The air gap faces the contact at the side face on the contact side via the insulating layer.

Abstract translation: 栅电极和侧壁被绝缘层覆盖。 接触通过绝缘层并连接到扩散层。 然后，气隙位于侧壁和接触件之间。 气隙经由绝缘层与接触侧的侧面接触。

公开(公告)号：US20150318201A1

公开(公告)日：2015-11-05

申请号：US14798284

申请日：2015-07-13

Applicant: Renesas Electronics Corporation

Inventor： Tatsuya Usami

IPC: H01L21/768 ,  H01L21/3205 ,  H01L21/033 ,  H01L21/02 ,  H01L21/311

CPC classification number: H01L21/76811 ,  H01L21/02164 ,  H01L21/02167 ,  H01L21/0217 ,  H01L21/02532 ,  H01L21/02592 ,  H01L21/02595 ,  H01L21/0332 ,  H01L21/0337 ,  H01L21/31144 ,  H01L21/32051 ,  H01L21/76813 ,  H01L21/76877

Abstract: A method of manufacturing a semiconductor device, including (a) forming an interlayer insulating film over a semiconductor substrate; (b) forming a third hard mask film over the interlayer insulating film; (c) forming a second hard mask film over the third hard mask film; (d) forming a first hard mask film over the second hard mask film; (e) after the step (d), forming a first opening in the first hard mask film and a second opening in the second hard mask film by etching the first and second hard mask films, respectively; (f) after the step (e), etching the first hard mask film so as to expand the first opening; and (g) after the step (f), etching the third hard mask film and a part of the interlayer insulating film in the second opening by using the second hard mask film as a mask.

Abstract translation: 一种制造半导体器件的方法，包括（a）在半导体衬底上形成层间绝缘膜; （b）在所述层间绝缘膜上形成第三硬掩模膜; （c）在所述第三硬掩模膜上形成第二硬掩模膜; （d）在所述第二硬掩模膜上形成第一硬掩模膜; （e）在步骤（d）之后，分别通过蚀刻第一和第二硬掩模膜在第一硬掩模膜中形成第一开口和第二硬掩模膜中的第二开口; （f）在步骤（e）之后，蚀刻第一硬掩模膜以使第一开口膨胀; 和（g）在步骤（f）之后，通过使用第二硬掩模膜作为掩模蚀刻第三硬掩模膜和第二开口中的部分层间绝缘膜。

公开(公告)号：US20150228586A1

公开(公告)日：2015-08-13

申请号：US14381572

申请日：2013-11-08

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Tatsuya Usami ,  Yukio Miura ,  Hideaki Tsuchiya

IPC: H01L23/532 ,  H01L21/02 ,  H01L21/263 ,  H01L21/265 ,  H01L21/768 ,  H01L23/528

CPC classification number: H01L23/528 ,  H01L21/02074 ,  H01L21/02126 ,  H01L21/02211 ,  H01L21/02271 ,  H01L21/02274 ,  H01L21/263 ,  H01L21/265 ,  H01L21/3105 ,  H01L21/31144 ,  H01L21/321 ,  H01L21/768 ,  H01L21/76802 ,  H01L21/76807 ,  H01L21/76808 ,  H01L21/76825 ,  H01L21/76826 ,  H01L21/76829 ,  H01L21/76831 ,  H01L21/76832 ,  H01L21/76834 ,  H01L21/76843 ,  H01L21/76859 ,  H01L21/76879 ,  H01L21/76883 ,  H01L23/5226 ,  H01L23/53228 ,  H01L23/53238 ,  H01L23/5329 ,  H01L23/53295 ,  H01L2924/0002 ,  H01L2924/00

Abstract: A semiconductor device includes an interlayer insulating film INS2, adjacent Cu wirings M1W formed in the interlayer insulating film INS2, and an insulating barrier film BR1 which is in contact with a surface of the interlayer insulating film INS2 and surfaces of the Cu wirings M1W and covers the interlayer insulating film INS2 and the Cu wirings M1W. Between the adjacent Cu wirings M1W, the interlayer insulating film INS2 has a damage layer DM1 on its surface, and has an electric field relaxation layer ER1 having a higher nitrogen concentration than a nitrogen concentration of the damage layer DM1 at a position deeper than the damage layer DM1.

Abstract translation: 半导体器件包括层间绝缘膜INS2，形成在层间绝缘膜INS2中的相邻的Cu布线M1W和与层间绝缘膜INS2的表面接触的绝缘阻挡膜BR1和Cu布线M1W和盖的表面 层间绝缘膜INS2和Cu布线M1W。 在相邻的Cu配线M1W之间，层间绝缘膜INS2在其表面具有损伤层DM1，并且在比损伤深的位置具有比损伤层DM1的氮浓度高的氮浓度的电场缓和层ER1 层DM1。