公开(公告)号：US20200373244A1

公开(公告)日：2020-11-26

申请号：US16556816

申请日：2019-08-30

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Myung Sam KANG ,  Yong Koon LEE ,  Young Gwan KO ,  Young Chan KO ,  Moon Il KIM

IPC: H01L23/538 ,  H01L23/66 ,  H01L23/31 ,  H01L23/367 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56 ,  H01Q1/38

Abstract: A semiconductor package includes a frame having first and second through-portions, first and second semiconductor chips, respectively in the first and second through-portions, each having a first surface, on which a connection pad is disposed, a first encapsulant covering at least a portion of the first and second semiconductor chips, a first connection member on the first and second semiconductor chips including a first redistribution layer electrically connected to the connection pads of the first and second semiconductor chips and a heat dissipation pattern layer, at least one passive component above the first semiconductor chip on the first connection member, and at least one heat dissipation structure above the second semiconductor chip on the first connection member and connected to the heat dissipation pattern layer.

公开(公告)号：US20190122994A1

公开(公告)日：2019-04-25

申请号：US15950000

申请日：2018-04-10

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Yong Koon LEE ,  Jin Gu KIM ,  Jin Su KIM

IPC: H01L23/552 ,  H01L23/31 ,  H01L23/538 ,  H01L23/00 ,  H01L21/48 ,  H01L21/56

Abstract: A semiconductor package includes a semiconductor chip having an active surface having connection pads disposed thereon and an inactive surface opposing the active surface; an encapsulant encapsulating at least a portion of the semiconductor chip; and a connection member including an insulating layer disposed on the active surface of the semiconductor chip, a signal pattern disposed in the insulating layer, first ground patterns disposed to be spaced apart from the signal pattern on both sides of the signal pattern, second ground patterns disposed to be spaced apart from the signal pattern in an upper portion and a lower portion of the signal pattern, and line vias connecting the first ground patterns and the second ground patterns to each other and having a line shape.

公开(公告)号：US20170287839A1

公开(公告)日：2017-10-05

申请号：US15353249

申请日：2016-11-16

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Yong Koon LEE ,  Yong Jin SEOL ,  Sang Kyu LEE

IPC: H01L23/538 ,  H01L21/768 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56

CPC classification number: H01L23/5389 ,  H01L21/56 ,  H01L21/76802 ,  H01L21/76877 ,  H01L21/76895 ,  H01L23/13 ,  H01L23/145 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5386 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/2101 ,  H01L2224/214

Abstract: A fan-out semiconductor package includes a redistribution layer, the redistribution layer including a first insulating layer, a first wiring disposed on the first insulating layer, a second insulating layer disposed on the first insulating layer and covering the first wiring, a line via passing through the second insulating layer continuously and connected to the first wiring, and a second wiring disposed on the second insulating layer and connected to the line via; a semiconductor chip disposed on one side of the redistribution layer, and having an electrode pad electrically connected to the first wiring, the second wiring, and the line via; and an encapsulant disposed on the one side of the redistribution layer, and encapsulating the semiconductor chip.

公开(公告)号：US20170373035A1

公开(公告)日：2017-12-28

申请号：US15478374

申请日：2017-04-04

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Yong Jin SEOL ,  Yong Koon LEE

IPC: H01L23/00 ,  H01L25/18

CPC classification number: H01L24/25 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/24 ,  H01L25/105 ,  H01L25/18 ,  H01L2224/02373 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/06131 ,  H01L2224/06135 ,  H01L2224/06139 ,  H01L2224/06177 ,  H01L2224/06182 ,  H01L2224/13024 ,  H01L2224/14131 ,  H01L2224/14135 ,  H01L2224/14181 ,  H01L2224/16227 ,  H01L2224/24105 ,  H01L2224/24226 ,  H01L2224/25171 ,  H01L2224/2518 ,  H01L2924/19102

Abstract: A fan-out semiconductor package module includes: a fan-out semiconductor package including a first interconnection member having a through-hole, a semiconductor chip disposed in the through-hole, an encapsulant encapsulating at least portions of the first interconnection member and the semiconductor chip, a second interconnection member disposed on the first interconnection member and the semiconductor chip, a third interconnection member disposed on the encapsulant, first connection terminals disposed on the second interconnection member, and second connection terminals disposed on the third interconnection member, the first to third interconnection members including, respectively, redistribution layers electrically connected to connection pads of the semiconductor chip; and a component package stacked on the fan-out semiconductor package and including a wiring substrate connected to the second interconnection member through the first connection terminals and a plurality of mounted components mounted on the wiring substrate.

公开(公告)号：US20180158791A1

公开(公告)日：2018-06-07

申请号：US15870593

申请日：2018-01-12

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Yong Jin SEOL ,  Yong Koon LEE

IPC: H01L23/00 ,  H01L25/18

CPC classification number: H01L24/25 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/24 ,  H01L25/105 ,  H01L25/18 ,  H01L2224/02373 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/06131 ,  H01L2224/06135 ,  H01L2224/06139 ,  H01L2224/06177 ,  H01L2224/06182 ,  H01L2224/13024 ,  H01L2224/14131 ,  H01L2224/14135 ,  H01L2224/14181 ,  H01L2224/16227 ,  H01L2224/24105 ,  H01L2224/24226 ,  H01L2224/25171 ,  H01L2224/2518 ,  H01L2924/19102

Abstract: A fan-out semiconductor package module includes: a fan-out semiconductor package including a first interconnection member having a through-hole, a semiconductor chip disposed in the through-hole, an encapsulant encapsulating at least portions of the first interconnection member and the semiconductor chip, a second interconnection member disposed on the first interconnection member and the semiconductor chip, a third interconnection member disposed on the encapsulant, first connection terminals disposed on the second interconnection member, and second connection terminals disposed on the third interconnection member, the first to third interconnection members including, respectively, redistribution layers electrically connected to connection pads of the semiconductor chip; and a component package stacked on the fan-out semiconductor package and including a wiring substrate connected to the second interconnection member through the first connection terminals and a plurality of mounted components mounted on the wiring substrate.

公开(公告)号：US20180061801A1

公开(公告)日：2018-03-01

申请号：US15789685

申请日：2017-10-20

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Yong Jin SEOL ,  Yong Koon LEE

IPC: H01L23/00 ,  H01L25/18

CPC classification number: H01L24/25 ,  H01L24/06 ,  H01L24/13 ,  H01L24/14 ,  H01L24/16 ,  H01L24/24 ,  H01L25/105 ,  H01L25/18 ,  H01L2224/02373 ,  H01L2224/02379 ,  H01L2224/02381 ,  H01L2224/0401 ,  H01L2224/04105 ,  H01L2224/06131 ,  H01L2224/06135 ,  H01L2224/06139 ,  H01L2224/06177 ,  H01L2224/06182 ,  H01L2224/13024 ,  H01L2224/14131 ,  H01L2224/14135 ,  H01L2224/14181 ,  H01L2224/16227 ,  H01L2224/24105 ,  H01L2224/24226 ,  H01L2224/25171 ,  H01L2224/2518 ,  H01L2924/19102

Abstract: A fan-out semiconductor package module includes: a fan-out semiconductor package including a first interconnection member having a through-hole, a semiconductor chip disposed in the through-hole, an encapsulant encapsulating at least portions of the first interconnection member and the semiconductor chip, a second interconnection member disposed on the first interconnection member and the semiconductor chip, a third interconnection member disposed on the encapsulant, first connection terminals disposed on the second interconnection member, and second connection terminals disposed on the third interconnection member, the first to third interconnection members including, respectively, redistribution layers electrically connected to connection pads of the semiconductor chip; and a component package stacked on the fan-out semiconductor package and including a wiring substrate connected to the second interconnection member through the first connection terminals and a plurality of mounted components mounted on the wiring substrate.

公开(公告)号：US20170287825A1

公开(公告)日：2017-10-05

申请号：US15352060

申请日：2016-11-15

Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.

Inventor： Yong Koon LEE ,  Sang Kyu LEE ,  Yong Jin SEOL

IPC: H01L23/498 ,  H01L23/29 ,  H01L23/31 ,  H01L21/56 ,  H01L23/00 ,  H01L23/367 ,  H01L21/48 ,  H01L23/552 ,  H01L23/538

CPC classification number: H01L23/49827 ,  H01L21/56 ,  H01L23/16 ,  H01L23/29 ,  H01L23/3107 ,  H01L23/3128 ,  H01L23/49816 ,  H01L23/49822 ,  H01L23/49838 ,  H01L23/5384 ,  H01L23/5389 ,  H01L23/552 ,  H01L24/19 ,  H01L24/20 ,  H01L2224/02379 ,  H01L2224/04105 ,  H01L2224/05569 ,  H01L2224/05572 ,  H01L2224/12105 ,  H01L2224/16227 ,  H01L2224/16235 ,  H01L2224/16238 ,  H01L2224/24011 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2924/15311 ,  H01L2924/19041 ,  H01L2924/19042 ,  H01L2924/19043 ,  H01L2924/19105 ,  H01L2924/3025

Abstract: A fan-out semiconductor package include a frame having a through hole; a semiconductor chip disposed in the through hole, and having an active surface, an inactive surface, and a side surface; an encapsulant disposed on one sides of the frame and the semiconductor chip, and in a space between the frame and the semiconductor chip in the through hole, a first conductive layer disposed on a sidewall of the through hole, a second conductive layer disposed on one side of the frame, and connected to the first conductive layer, a line via passing through the encapsulant, and connected to the second conductive layer, and a third conductive layer covering at least the inactive surface of the semiconductor chip on the encapsulant, and connected to the line via.