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    SEMICONDUCTOR MEMORY DEVICES
    1.
    发明公开
    SEMICONDUCTOR MEMORY DEVICES 审中-公开

    公开(公告)号：US20240015978A1

    公开(公告)日：2024-01-11

    申请号：US18320816

    申请日：2023-05-19

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Siyeon Cho ,  Taeyoung Kim ,  Hyunmog Park ,  Bongyong Lee ,  Yukio Hayakawa

    IPC: H10B51/20 ,  H10B51/10 ,  H01L23/528

    CPC classification number: H10B51/20 ,  H10B51/10 ,  H01L23/5283

    Abstract: Disclosed are semiconductor memory devices and electronic systems including the same. The semiconductor memory device may include a vertical channel perpendicular to a top surface of a substrate, word lines disposed on a first side of the vertical channel and vertically stacked on the substrate, back-gate electrodes disposed on a second side of the vertical channel and vertically stacked on the substrate, a ferroelectric layer disposed between the word lines and the first side of the vertical channel, a first intermediate insulating layer disposed between the ferroelectric layer and the first side of the vertical channel, and a second intermediate insulating layer disposed between the back-gate electrodes and the second side of the vertical channel.

    Three-dimensional semiconductor memory devices
    2.
    发明授权
    Three-dimensional semiconductor memory devices 有权

    公开(公告)号：US10998334B2

    公开(公告)日：2021-05-04

    申请号：US16536842

    申请日：2019-08-09

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Bongyong Lee ,  Minkyung Bae ,  Myunghun Woo

    IPC: H01L27/11582 ,  H01L27/11565 ,  H01L23/522 ,  H01L21/225 ,  H01L21/3205

    Abstract: A three-dimensional semiconductor memory device may include a stack including gate electrodes sequentially stacked on a substrate and a vertical structure penetrating the stack. The vertical structure may include a vertical channel portion, a charge storing structure on an outer side surface of the vertical channel portion, and a pad. The pad may include a first pad portion disposed in an internal space surrounded by the vertical channel portion and a second pad portion provided on the first pad portion and extended onto a top surface of the charge storing structure. A portion of the first pad portion may be disposed at the same level as an uppermost electrode of the gate electrodes.

    Nonvolatile memory device, an operating method thereof, and a storage system including the nonvolatile memory device
    4.
    发明授权
    Nonvolatile memory device, an operating method thereof, and a storage system including the nonvolatile memory device 有权

    公开(公告)号：US10923195B2

    公开(公告)日：2021-02-16

    申请号：US16686327

    申请日：2019-11-18

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Minkyung Bae ,  Tae Hun Kim ,  Myunghun Woo ,  Bongyong Lee ,  Doohee Hwang

    IPC: G11C11/34 ,  G11C16/14 ,  G11C16/08 ,  G11C16/04 ,  H01L27/11582

    Abstract: An operating method of a nonvolatile memory device which includes a cell string including a plurality of cell transistors connected in series between a bit line and a common source line and stacked in a direction perpendicular to a substrate, the method including: programming an erase control transistor of the plurality of cell transistors; and after the erase control transistor is programmed, applying an erase voltage to the common source line or the bit line and applying an erase control voltage to an erase control line connected to the erase control transistor, wherein the erase control voltage is less than the erase voltage and greater than a ground voltage, and wherein the erase control transistor is between a ground selection transistor of the plurality of cell transistors and the common source line or between a string selection transistor of the plurality of cell transistors and the bit line.

    METHODS OF FABRICATING THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES USING DIRECT STRAPPING LINE CONNECTIONS
    5.
    发明申请
    METHODS OF FABRICATING THREE-DIMENSIONAL SEMICONDUCTOR MEMORY DEVICES USING DIRECT STRAPPING LINE CONNECTIONS 审中-公开
    使用直接连接线连接制作三维半导体存储器件的方法

    公开(公告)号：US20140349453A1

    公开(公告)日：2014-11-27

    申请号：US14455429

    申请日：2014-08-08

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Bongyong Lee ,  Sang-Hoon Kim ,  Ae-Jeong Lee ,  Dongchan Kim

    IPC: H01L27/115

    CPC classification number: H01L27/11551 ,  H01L27/11556 ,  H01L27/11578 ,  H01L27/11582

    Abstract: Memory devices include a plurality of elongate gate stacks extending in parallel on a substrate and at least one insulation region disposed in a trench between adjacent ones of the gate stacks. The at least one insulation region has linear first portions having a first width and widened second portions having a second width greater than the first width. A common source region is disposed in the substrate underlying the at least one insulation region. The devices further include respective conductive plugs passing through respective ones of the widened second portions of the at least one insulation region and electrically connected to the common source region and at least one strapping line disposed on the conductive plugs between the adjacent ones of the gate stacks and in direct contact with the conductive plugs.

    Abstract translation: 存储器件包括在衬底上平行延伸的多个细长栅极叠层和设置在相邻栅极叠层之间沟槽中的至少一个绝缘区域。 所述至少一个绝缘区具有具有第一宽度的线性第一部分和具有大于第一宽度的第二宽度的加宽的第二部分。 公共源极区域设置在至少一个绝缘区域下方的衬底中。 这些器件还包括各自的导电插塞，其穿过至少一个绝缘区域的加宽的第二部分中的相应导电插塞并且电连接到公共源极区域，以及设置在相邻栅极叠层之间的导电插塞上的至少一个捆扎线 并与导电插头直接接触。

    Three-dimensional semiconductor memory devices
    8.
    发明授权
    Three-dimensional semiconductor memory devices 有权

    公开(公告)号：US10790358B2

    公开(公告)日：2020-09-29

    申请号：US16515412

    申请日：2019-07-18

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Moorym Choi ,  Bongyong Lee ,  Junhee Lim

    IPC: H01L27/00 ,  H01L29/10 ,  H01L29/78 ,  H01L27/11524 ,  H01L27/11556 ,  H01L27/1157 ,  H01L27/11582

    Abstract: A three-dimensional semiconductor memory device includes common source regions, an electrode structure between the common source regions, first channel structures penetrating the electrode structure, and second channel structures between the first channel structures and penetrating the electrode structures. The electrode structure includes electrodes vertically stacked on a substrate. The first channel structures include a first semiconductor pattern and a first vertical insulation layer. The second channel structures include a second vertical insulation layer surrounding a second semiconductor pattern. The second vertical insulation layer has a bottom surface lower than a bottom surface of the first vertical insulation layer.

    Magnetic memory device and method of operating the same
    10.
    发明授权
    Magnetic memory device and method of operating the same 有权

    公开(公告)号：US12290007B2

    公开(公告)日：2025-04-29

    申请号：US17966183

    申请日：2022-10-14

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Siyeon Cho ,  Taeyoung Kim ,  Hyunmog Park ,  Bongyong Lee ,  Yukio Hayakawa

    IPC: G11C11/15 ,  G11C11/16 ,  G11C11/18 ,  H10B61/00 ,  H10N50/85 ,  H10N52/00 ,  H10N52/80

    Abstract: A magnetic memory device includes a loop-type magnetic track having a first part and a second part that are arranged in a counterclockwise direction, a first conductive line on a top surface of the first part, and a second conductive line on a bottom surface of the second part. The magnetic track includes a lower magnetic layer, a spacer layer, and an upper magnetic layer that are sequentially stacked. Each of the first and second conductive lines includes heavy metal. Each of the first and second conductive lines is configured to generate spin-orbit torque caused by current that flows therein. The spin-orbit torque causes magnetic domains in the magnetic track to move in a clockwise direction or in the counterclockwise direction.

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