公开(公告)号：US12302561B2

公开(公告)日：2025-05-13

申请号：US17354445

申请日：2021-06-22

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Minjun Kang ,  Byunggon Park ,  Joongshik Shin

IPC: H01L27/11582 ,  H01L27/11529 ,  H01L27/11556 ,  H01L27/11573 ,  H10B41/27 ,  H10B41/41 ,  H10B43/27 ,  H10B43/40

Abstract: A semiconductor device including a gate electrode structure on a substrate and including gate electrodes spaced apart from each other in a first direction, each gate electrode extending in a second direction; a memory channel structure extending through the gate electrode structure on the substrate, the memory channel structure including a channel extending in the first direction; a charge storage structure surrounding an outer sidewall of the channel; a first filling pattern filling an inner space formed by the channel; and a first capping pattern on the channel and the first filling pattern; and a dummy charge storage structure extending through the gate electrode structure on the substrate, the dummy charge storage structure including a second filling pattern extending in the first direction; a dummy charge storage structure surrounding an outer sidewall of the second filling pattern; and a second capping pattern on the second filling pattern.

公开(公告)号：US11980028B2

公开(公告)日：2024-05-07

申请号：US17343330

申请日：2021-06-09

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Geunwon Lim ,  Minjun Kang ,  Byunggon Park ,  Joongshik Shin

IPC: H10B43/27 ,  G11C7/18 ,  H01L23/528 ,  H10B41/10 ,  H10B41/27 ,  H10B41/40 ,  H10B43/10 ,  H10B43/40

CPC classification number: H10B41/40 ,  G11C7/18 ,  H01L23/5283 ,  H10B41/10 ,  H10B41/27 ,  H10B43/10 ,  H10B43/27 ,  H10B43/40

Abstract: A semiconductor includes a lower structure and a stack structure having interlayer insulating layers and horizontal layers alternately stacked on the lower structure. A first dam vertical structure penetrates the stack structure. The first dam vertical structure divides the stack structure into a gate stack region and an insulator stack region. The horizontal layers include gate horizontal layers in the gate stack region and insulating horizontal layers in the insulator stack region. A memory vertical structure and a supporter vertical structure penetrate the gate stack region. Separation structures penetrate the gate stack region. One separation structure includes a first side surface, a second side surface not perpendicular to the first side surface, and a connection side surface extending from the first side surface to the second side surface. The connection side surface is higher than an uppermost gate horizontal layer of the gate horizontal layers.