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公开(公告)号:US10114562B2
公开(公告)日:2018-10-30
申请号:US14488037
申请日:2014-09-16
Applicant: SANDISK TECHNOLOGIES LLC
Inventor: Narendhiran Chinnaanangur Ravimohan , Muralitharan Jayaraman , Abhijeet Manohar , Alan Bennett
IPC: G06F3/06 , G06F12/0804 , G06F12/0866 , G06F12/02
Abstract: In a multi-plane non-volatile memory, good blocks of different planes are linked for parallel operation for storing long host writes. Where bad blocks in one or more planes result in unlinked blocks, the unlinked blocks are configured for individual operation to store short host writes and/or memory system management data. Unlinked blocks may be configured as Single Level Cell (SLC) blocks while linked blocks may be configured as SLC blocks or Multi Level Cell (MLC) blocks.
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公开(公告)号:US20180293014A1
公开(公告)日:2018-10-11
申请号:US15483185
申请日:2017-04-10
Applicant: SanDisk Technologies LLC
Inventor: Narendhiran Chinnaanangur Ravimohan , Muralitharan Jayaraman , Balakumar Rajendran , Satya Kesav Gundabathula , Ramkumar Ramamurthy , Rohit Sathyanarayan
CPC classification number: G06F3/0631 , G06F3/061 , G06F3/0626 , G06F3/0653 , G06F3/0679 , G11C11/5628 , G11C16/10 , G11C16/30 , G11C16/32 , G11C16/3459 , G11C2211/5641
Abstract: A memory system may be configured to perform immediate folding of data from a low storage density area to a high storage density area. A low storage density target area may be monitored, and when a capacity of the low storage density target area reaches a threshold level, data stored in the low storage density target area may be folded to an associated high storage density target area. The memory system may utilize a pointer system to manage the folding of data. The pointer system may also be utilized for read operations in order to avoid updating address mapping tables for both the low storage density and the high storage density areas.
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公开(公告)号:US10268387B2
公开(公告)日:2019-04-23
申请号:US15398495
申请日:2017-01-04
Applicant: SanDisk Technologies LLC
Inventor: Narendhiran Cr , Satya Kesav Gundabathula , Muralitharan Jayaraman , Chittoor Devarajan Sunilkumar , Satrajit Chakraborty
IPC: G06F3/06
Abstract: Technology is described herein for performing memory array operations in multiple memory dies in parallel. The memory dies, or groups of non-volatile memory cells on the memory dies, may exhibit different performance times for memory array operations. For example, non-volatile memory cells on one memory die may program more slowly than those on another memory die. The performance times of the memory dies (or groups of the memory cells on different memory dies) may be characterized relative to one another. Memory dies having similar performance times may be placed into the same meta-groups. Meta-groups may be formed at the die, zone, or block level. The meta-groups can be re-formed over the lifetime of the memory system, which can account for changes in performance times over the lifetime of the memory system.
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公开(公告)号:US10275170B2
公开(公告)日:2019-04-30
申请号:US15483185
申请日:2017-04-10
Applicant: SanDisk Technologies LLC
Inventor: Narendhiran Chinnaanangur Ravimohan , Muralitharan Jayaraman , Balakumar Rajendran , Satya Kesav Gundabathula , Ramkumar Ramamurthy , Rohit Sathyanarayan
Abstract: A memory system may be configured to perform immediate folding of data from a low storage density area to a high storage density area. A low storage density target area may be monitored, and when a capacity of the low storage density target area reaches a threshold level, data stored in the low storage density target area may be folded to an associated high storage density target area. The memory system may utilize a pointer system to manage the folding of data. The pointer system may also be utilized for read operations in order to avoid updating address mapping tables for both the low storage density and the high storage density areas.
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公开(公告)号:US20180188956A1
公开(公告)日:2018-07-05
申请号:US15398495
申请日:2017-01-04
Applicant: SanDisk Technologies LLC
Inventor: Narendhiran CR , Satya Kesav Gundabathula , Muralitharan Jayaraman , Chittoor Devarajan Sunilkumar , Satrajit Chakraborty
IPC: G06F3/06
CPC classification number: G06F3/061 , G06F3/0644 , G06F3/0653 , G06F3/0659 , G06F3/0688
Abstract: Technology is described herein for performing memory array operations in multiple memory dies in parallel. The memory dies, or groups of non-volatile memory cells on the memory dies, may exhibit different performance times for memory array operations. For example, non-volatile memory cells on one memory die may program more slowly than those on another memory die. The performance times of the memory dies (or groups of the memory cells on different memory dies) may be characterized relative to one another. Memory dies having similar performance times may be placed into the same meta-groups. Meta-groups may be formed at the die, zone, or block level. The meta-groups can be re-formed over the lifetime of the memory system, which can account for changes in performance times over the lifetime of the memory system.
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