公开(公告)号：US11304311B2

公开(公告)日：2022-04-12

申请号：US17080524

申请日：2020-10-26

Applicant: SANMINA CORPORATION

Inventor： Shinichi Iketani ,  Drew Doblar

IPC: H05K1/11 ,  H05K1/02 ,  H05K3/42

Abstract: A multilayer printed circuit board is provided having a first conductive layer and a first plating resist selectively positioned within the first conductive layer. A second plating resist may be selectively positioned within a second conductive layer. A through hole extends through the first plating resist in the first conductive layer and the second plating resist in the second conductive layer. An interior surface of the through hole is plated with a conductive material except along a length between the first plating resist and the second plating resist. This forms a partitioned plated through hole having a first via segment electrically isolated from a second via segment.

公开(公告)号：US20210153360A1

公开(公告)日：2021-05-20

申请号：US17080524

申请日：2020-10-26

Applicant: SANMINA CORPORATION

Inventor： Shinichi Iketani ,  Drew Doblar

IPC: H05K3/42 ,  H05K1/11

Abstract: A multilayer printed circuit board is provided having a first conductive layer and a first plating resist selectively positioned within the first conductive layer. A second plating resist may be selectively positioned within a second conductive layer. A through hole extends through the first plating resist in the first conductive layer and the second plating resist in the second conductive layer. An interior surface of the through hole is plated with a conductive material except along a length between the first plating resist and the second plating resist. This forms a partitioned plated through hole having a first via segment electrically isolated from a second via segment.

公开(公告)号：US10820427B2

公开(公告)日：2020-10-27

申请号：US16518967

申请日：2019-07-22

Applicant: SANMINA CORPORATION

Inventor： Shinichi Iketani ,  Drew Doblar

IPC: H05K3/42 ,  H05K1/11 ,  H05K1/02

Abstract: A multilayer printed circuit board is provided having a first conductive layer and a first plating resist selectively positioned within the first conductive layer. A second plating resist may be selectively positioned within a second conductive layer. A through hole extends through the first plating resist in the first conductive layer and the second plating resist in the second conductive layer. An interior surface of the through hole is plated with a conductive material except along a length between the first plating resist and the second plating resist. This forms a partitioned plated through hole having a first via segment electrically isolated from a second via segment.

公开(公告)号：US20200015364A1

公开(公告)日：2020-01-09

申请号：US16518967

申请日：2019-07-22

Applicant: SANMINA CORPORATION

Inventor： Shinichi Iketani ,  Drew Doblar

IPC: H05K3/42 ,  H05K1/11

Abstract: A multilayer printed circuit board is provided having a first conductive layer and a first plating resist selectively positioned within the first conductive layer. A second plating resist may be selectively positioned within a second conductive layer. A through hole extends through the first plating resist in the first conductive layer and the second plating resist in the second conductive layer. An interior surface of the through hole is plated with a conductive material except along a length between the first plating resist and the second plating resist. This forms a partitioned plated through hole having a first via segment electrically isolated from a second via segment.