公开(公告)号：US20180098426A1

公开(公告)日：2018-04-05

申请号：US15723086

申请日：2017-10-02

Applicant: SANMINA CORPORATION

Inventor： Shinichi Iketani ,  Dale Kersten ,  George Dudnikov, JR.

IPC: H05K1/11 ,  H05K1/03 ,  H05K3/42

Abstract: A multilayer printed circuit board is provided having a first dielectric layer and a first plating resist selectively positioned in the first dielectric layer. A second plating resist may be selectively positioned in the first dielectric layer or a second dielectric layer, the second plating resist separate from the first plating resist. A through hole extends through the first dielectric layer, the first plating resist, and the second plating resist. An interior surface of the through hole is plated with a conductive material except along a length between the first plating resist and the second plating resist. This forms a partitioned plated through hole having a first via segment electrically isolated from a second via segment.

公开(公告)号：US20200383204A1

公开(公告)日：2020-12-03

申请号：US16883671

申请日：2020-05-26

Applicant: Sanmina Corporation

Inventor： Shinichi Iketani ,  Dale Kersten ,  George Dudnikov, JR.

IPC: H05K1/11 ,  H05K1/03 ,  H05K3/42

Abstract: A multilayer printed circuit board is provided having a first dielectric layer and a first plating resist selectively positioned in the first dielectric layer. A second plating resist may be selectively positioned in the first dielectric layer or a second dielectric layer, the second plating resist separate from the first plating resist. A through hole extends through the first dielectric layer, the first plating resist, and the second plating resist. An interior surface of the through hole is plated with a conductive material except along a length between the first plating resist and the second plating resist. This forms a partitioned plated through hole having a first via segment electrically isolated from a second via segment.