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公开(公告)号：US10789207B2
公开(公告)日：2020-09-29
申请号：US16233644
申请日：2018-12-27
Applicant: SAS Institute Inc.
Inventor： Brian Payton Bowman , Jeff Ira Cleveland, III
IPC: G06F12/00 , G06F16/13 , G06F3/06 , G06F21/60 , G06F16/22 , G06F16/27 , G06F9/50 , G06F12/02 , G06F16/182 , G06F13/00 , G06F13/28
Abstract: An apparatus includes a processor component to: transmit node device identifiers to multiple node devices to define an ordering thereamong; following block exchanges redistributing the subsets among a reduced number of node devices, receive sizes of blocks or sub-blocks of data within each subset from the reduced number of node devices; based on the received sizes, generate map data organized to define an ordering among the blocks stemming from the ordering among the multiple node devices; determine whether the total size of the map data and metadata, together, exceeds a minimum size for data transmissions to storage device(s); and in response to the total size exceeding the minimum size, form the map data and metadata into segment(s) that each fit the minimum size and a maximum size, and transmit the segment(s) at least partially in parallel with other segments of the blocks transmitted by the reduced number of node devices.
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Patent Agency Ranking
公开(公告)号：US20190129887A1
公开(公告)日：2019-05-02
申请号：US16233400
申请日：2018-12-27
Applicant: SAS Institute Inc.
Inventor： Brian Payton Bowman , Jeff Ira Cleveland, III
CPC classification number: G06F16/137 , G06F3/0604 , G06F3/061 , G06F3/064 , G06F3/0643 , G06F3/0644 , G06F3/067 , G06F9/5072 , G06F9/5077 , G06F12/0292 , G06F16/1827 , G06F16/22 , G06F16/278 , G06F21/602 , G06F2212/1016 , G06F2212/1056 , G06F2212/154 , G06F2212/262 , G06F2212/263 , H05K999/99
Abstract: An apparatus includes a processor component to receive a node device identifier defining an ordering among multiple node devices and among multiple blocks of data distributed among the multiple node devices, and transmit a size of a first subset of the multiple blocks stored within the node device to a control device. In response to receiving instructions to receive a second subset from another node device, perform operations including: receive and store the second subset; group the blocks of data of the first and second subsets into multiple segments in an order that corresponds to the ordering among the multiple blocks, wherein each segment is sized to fit minimum and maximum sizes for transmission to storage device(s); transmit the multiple segments to the storage device(s); and relay multiple segment identifiers from the storage device(s) to the control device in an order corresponding to the ordering among the multiple segments.
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公开(公告)号：US10402372B2
公开(公告)日：2019-09-03
申请号：US16233400
申请日：2018-12-27
Applicant: SAS Institute Inc.
Inventor： Brian Payton Bowman , Jeff Ira Cleveland, III
IPC: G06F12/00 , G06F16/13 , G06F3/06 , G06F21/60 , G06F16/22 , G06F16/27 , G06F9/50 , G06F12/02 , G06F16/182 , G06F13/00 , G06F13/28
Abstract: An apparatus includes a processor component to receive a node device identifier defining an ordering among multiple node devices and among multiple blocks of data distributed among the multiple node devices, and transmit a size of a first subset of the multiple blocks stored within the node device to a control device. In response to receiving instructions to receive a second subset from another node device, perform operations including: receive and store the second subset; group the blocks of data of the first and second subsets into multiple segments in an order that corresponds to the ordering among the multiple blocks, wherein each segment is sized to fit minimum and maximum sizes for transmission to storage device(s); transmit the multiple segments to the storage device(s); and relay multiple segment identifiers from the storage device(s) to the control device in an order corresponding to the ordering among the multiple segments.
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公开(公告)号：US10311023B1
公开(公告)日：2019-06-04
申请号：US16233573
申请日：2018-12-27
Applicant: SAS Institute Inc.
Inventor： Brian Payton Bowman , Jeff Ira Cleveland, III
IPC: G06F12/00 , G06F16/13 , G06F3/06 , G06F21/60 , G06F16/22 , G06F16/27 , G06F9/50 , G06F12/02 , G06F16/182 , G06F13/00 , G06F13/28
CPC classification number: G06F16/137 , G06F3/0604 , G06F3/061 , G06F3/064 , G06F3/0643 , G06F3/0644 , G06F3/067 , G06F9/5072 , G06F9/5077 , G06F12/0292 , G06F16/1827 , G06F16/22 , G06F16/278 , G06F21/602 , G06F2212/1016 , G06F2212/1056 , G06F2212/154 , G06F2212/262 , G06F2212/263 , H05K999/99
Abstract: An apparatus of includes a processor component to: transmit node device identifiers to multiple node devices to define an ordering thereamong and among subsets of multiple blocks of data distributed thereamong; receive sizes of the subsets from the multiple node devices; derive block exchanges among the multiple node device based on the sizes and a minimum size imposed on data transmissions to storage device(s); and transmit a block exchange vector that describes the block exchanges to the multiple node devices, wherein: the subsets remain distributed among a reduced number of the multiple node devices following the block exchanges; at least all node devices of the reduced number but one stores an amount of the blocks of data exceeding the minimum size; and the block exchanges are all lower-order to higher-order node device transfers, or all higher-order to lower-order node device transfers.
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公开(公告)号：US20190197021A1
公开(公告)日：2019-06-27
申请号：US16233573
申请日：2018-12-27
Applicant: SAS Institute Inc.
Inventor： Brian Payton Bowman , Jeff Ira Cleveland, III
CPC classification number: G06F16/137 , G06F3/0604 , G06F3/061 , G06F3/064 , G06F3/0643 , G06F3/0644 , G06F3/067 , G06F9/5072 , G06F9/5077 , G06F12/0292 , G06F16/1827 , G06F16/22 , G06F16/278 , G06F21/602 , G06F2212/1016 , G06F2212/1056 , G06F2212/154 , G06F2212/262 , G06F2212/263 , H05K999/99
Abstract: An apparatus of includes a processor component to: transmit node device identifiers to multiple node devices to define an ordering thereamong and among subsets of multiple blocks of data distributed thereamong; receive sizes of the subsets from the multiple node devices; derive block exchanges among the multiple node device based on the sizes and a minimum size imposed on data transmissions to storage device(s); and transmit a block exchange vector that describes the block exchanges to the multiple node devices, wherein: the subsets remain distributed among a reduced number of the multiple node devices following the block exchanges; at least all node devices of the reduced number but one stores an amount of the blocks of data exceeding the minimum size; and the block exchanges are all lower-order to higher-order node device transfers, or all higher-order to lower-order node device transfers.
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公开(公告)号：US20190129888A1
公开(公告)日：2019-05-02
申请号：US16233644
申请日：2018-12-27
Applicant: SAS Institute Inc.
Inventor： Brian Payton Bowman , Jeff Ira Cleveland, III
Abstract: An apparatus includes a processor component to: transmit node device identifiers to multiple node devices to define an ordering thereamong; following block exchanges redistributing the subsets among a reduced number of node devices, receive sizes of blocks or sub-blocks of data within each subset from the reduced number of node devices; based on the received sizes, generate map data organized to define an ordering among the blocks stemming from the ordering among the multiple node devices; determine whether the total size of the map data and metadata, together, exceeds a minimum size for data transmissions to storage device(s); and in response to the total size exceeding the minimum size, form the map data and metadata into segment(s) that each fit the minimum size and a maximum size, and transmit the segment(s) at least partially in parallel with other segments of the blocks transmitted by the reduced number of node devices.
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