公开(公告)号：US20140297997A1

公开(公告)日：2014-10-02

申请号：US14143273

申请日：2013-12-30

Applicant: SAS INSTITUTE, INC.

Inventor： Jack Joseph Rouse ,  Leonardo Bezerra Lopes ,  Robert William Pratt

IPC: G06F9/30

CPC classification number: G06F8/45 ,  G06F8/41 ,  G06F8/423 ,  G06F8/4452 ,  G06F8/452 ,  G06F8/456 ,  G06F9/381

Abstract: Various embodiments are generally directed to techniques for reducing syntax requirements in application code to cause concurrent execution of multiple iterations of at least a portion of a loop thereof to reduce overall execution time in solving a large scale problem. At least one non-transitory machine-readable storage medium includes instructions that when executed by a computing device, cause the computing device to parse an application code to identify a loop instruction indicative of an instruction block that includes instructions that define a loop of which multiple iterations are capable of concurrent execution, the instructions including at least one call instruction to an executable routine capable of concurrent execution; and insert at least one coordinating instruction into an instruction sub-block of the instruction block to cause sequential execution of instructions of the instruction sub-block across the multiple iterations based on identification of the loop instruction. Other embodiments are described and claimed.

Abstract translation: 各种实施例通常涉及用于减少应用代码中的语法要求的技术，以引起并发执行其循环的至少一部分的多次迭代以减少解决大规模问题的总体执行时间。 至少一个非暂时的机器可读存储介质包括指令，当指令由计算设备执行时，使得计算设备解析应用代码以识别指示指令块的循环指令，该指令块包括指令，该指令定义了多个 迭代能够并发执行，所述指令包括至少一个能够并发执行的可执行例程的调用指令; 并且将至少一个协调指令插入到指令块的指令子块中，以基于循环指令的识别来跨越多次迭代顺序执行指令子块的指令。 描述和要求保护其他实施例。

公开(公告)号：US09448793B2

公开(公告)日：2016-09-20

申请号：US14936952

申请日：2015-11-10

Applicant: SAS Institute Inc.

Inventor： Matthew Victor Galati ,  Robert William Pratt ,  Leonardo Bezerra Lopes

IPC: G06F9/30 ,  G06F17/11

CPC classification number: G06F9/30007 ,  G06F9/30145 ,  G06F17/11

Abstract: Embodiments include techniques to receive computer-executable query instructions to solve a MILP problem, the query instructions including a first expression conveying an objective function and side constraint that define a master problem of the MILP problem, a second expression conveying a mapping of graph data to a graph, and a third expression conveying a selection of a graph-based algorithm to solve a subproblem of the MILP problem; a subproblem component to replace the third expression with a fourth expression during decomposition of the MILP problem, the fourth expression including instructions to implement the graph-based algorithm to solve the subproblem; and an execution control component to perform iterations of solving the MILP problem that include executing the first expression to derive a solution to the master problem; and executing the fourth expression to derive a solution to the subproblem based on the mapping and the master problem solution.

Abstract translation: 实施例包括用于接收计算机可执行查询指令以解决MILP问题的技术，所述查询指令包括传达目标函数的第一表达式和定义MILP问题的主要问题的边界约束，第二表达式将图形数据映射到 图形和第三表达式，其传达基于图的算法的选择以解决MILP问题的子问题; 一个子问题组件在MILP问题分解过程中用第四个表达式替换第三个表达式，第四个表达式包括实现基于图的算法来解决子问题的指令; 以及执行控制组件，用于执行解决包括执行所述第一表达式的MILP问题的迭代以导出所述主问题的解决方案; 并且基于映射和主问题解决方案执行第四表达式以导出子问题的解。

公开(公告)号：US20210157595A1

公开(公告)日：2021-05-27

申请号：US17105695

申请日：2020-11-27

Applicant: SAS Institute Inc.

Inventor： Jack Joseph Rouse ,  Robert William Pratt ,  Jack Carl Erickson ,  Manoj Keshavmurthi Chari

IPC: G06F9/38 ,  G06F9/46

Abstract: An apparatus includes a processor core to: receive a request to execute application code including a trigger instruction and an instruction block that reads a row of data values from a data structure and outputs a data value from a function using the row as input, wherein the data structure is divided into multiple portions and the trigger instruction indicates that multiple instances of the instruction block are to be executed concurrently; and in response to the request, and to identification of the instruction block and trigger instruction: generate multiple instances of a support block that causes independent repetitive execution of each instance of the instruction block until all rows of the corresponding portion of the data structure are used as input; assign instances of the instruction and support blocks to multiple processor cores; and provide each instance of the instruction block with the corresponding portion of the data structure.

公开(公告)号：US11645359B1

公开(公告)日：2023-05-09

申请号：US17938692

申请日：2022-10-07

Applicant: SAS Institute Inc.

Inventor： Wei Xu ,  Robert William Pratt ,  Natalia Summerville

IPC: G06F17/18

CPC classification number: G06F17/18

Abstract: A computing device selects a piecewise linear regression model for multivariable data. A hyperplane is fit to observation vectors using a linear multivariable regression. A baseline fit quality measure is computed for the fit hyperplane. For each independent variable, the observation vectors are sorted, contiguous segments to evaluate are defined, for each contiguous segment, a segment hyperplane is fit to the sorted observation vectors using a multivariable linear regression, path distances are computed between a first observation of the and a last observation of the sorted observation vectors based on a predefined number of segments, a shortest path associated with a smallest value of the computed path distances is selected, and a fit quality measure is computed for the selected shortest path. A best independent variable is selected from the independent variables based on having an extremum value for the computed fit quality measure.

公开(公告)号：US11113064B2

公开(公告)日：2021-09-07

申请号：US17105695

申请日：2020-11-27

Applicant: SAS Institute Inc.

Inventor： Jack Joseph Rouse ,  Robert William Pratt ,  Jared Carl Erickson ,  Manoj Keshavmurthi Chari

IPC: G06F9/38

Abstract: A processor core receives a request to execute application code including a trigger instruction and an instruction block that reads a row of data values from a data structure and outputs a data value from a function using the row as input. The data structure is divided into multiple portions and the trigger instruction indicates that multiple instances of the instruction block are to be executed concurrently. In response to the request and to identification of the instruction block and trigger instruction, the processor core generates multiple instances of a support block that causes independent repetitive execution of each instance of the instruction block until all rows of the corresponding portion of the data structure are used as input. The processor core assigns instances of the instruction and support blocks to multiple processor cores, and provides each instance of the instruction block with the corresponding portion of the data structure.

公开(公告)号：US09582256B2

公开(公告)日：2017-02-28

申请号：US14143273

申请日：2013-12-30

Applicant: SAS INSTITUTE, INC.

Inventor： Jack Joseph Rouse ,  Leonardo Bezerra Lopes ,  Robert William Pratt

IPC: G06F9/45 ,  G06F9/38

CPC classification number: G06F8/45 ,  G06F8/41 ,  G06F8/423 ,  G06F8/4452 ,  G06F8/452 ,  G06F8/456 ,  G06F9/381

Abstract: Various embodiments are generally directed to techniques for reducing syntax requirements in application code to cause concurrent execution of multiple iterations of at least a portion of a loop thereof to reduce overall execution time in solving a large scale problem. At least one non-transitory machine-readable storage medium includes instructions that when executed by a computing device, cause the computing device to parse an application code to identify a loop instruction indicative of an instruction block that includes instructions that define a loop of which multiple iterations are capable of concurrent execution, the instructions including at least one call instruction to an executable routine capable of concurrent execution; and insert at least one coordinating instruction into an instruction sub-block of the instruction block to cause sequential execution of instructions of the instruction sub-block across the multiple iterations based on identification of the loop instruction. Other embodiments are described and claimed.

Abstract translation: 各种实施例通常涉及用于减少应用代码中的语法要求的技术，以引起并发执行其循环的至少一部分的多次迭代以减少解决大规模问题的总体执行时间。 至少一个非暂时的机器可读存储介质包括指令，当指令由计算设备执行时，使得计算设备解析应用代码以识别指示指令块的循环指令，该指令块包括指令，该指令定义了多个 迭代能够并发执行，所述指令包括至少一个能够并发执行的可执行例程的调用指令; 并且将至少一个协调指令插入到指令块的指令子块中，以基于循环指令的识别来跨越多次迭代顺序执行指令子块的指令。 描述和要求保护其他实施例。

公开(公告)号：US20140222491A1

公开(公告)日：2014-08-07

申请号：US14168798

申请日：2014-01-30

Applicant: SAS Institute Inc.

Inventor： Teresa DePaola McMains ,  Thomas Burkhardt ,  Robert William Pratt

IPC: G06Q10/06

CPC classification number: G06Q10/06315 ,  G06Q10/087

Abstract: Systems and methods are provided for determining a distribution of each of a plurality of inner packs to a plurality of stores. Mismatch cost data and product demand data are received for the plurality of stores. A first inner pack quantity for distribution is determined based on the product demand data. A supply difference amount is determined, where the supply difference amount is a difference between the first inner pack quantity and the number of first inner packs available for distribution. A determination is made that adjusting the first inner pack quantity for the particular store based on the supply difference amount would have less effect on mismatch costs than other stores, and the first inner pack quantity is adjusted for the particular store based on the supply difference.

Abstract translation: 提供了用于确定多个内包装中的每一个到多个商店的分配的系统和方法。 为多个商店接收不匹配成本数据和产品需求数据。 基于产品需求数据确定用于分配的第一内包数量。 确定供给差量，其中供给差量是第一内包装数量和可分配的第一内包装件数量之间的差。 确定基于供给差量来调整特定商店的第一内包装数量将比其他商店对失配成本的影响较小，并且基于供应差异针对特定商店调整第一内包装数量。