公开(公告)号：US20130230954A1

公开(公告)日：2013-09-05

申请号：US13856649

申请日：2013-04-04

Applicant: SEMATECH, INC.

Inventor： Wei-Yip Loh ,  Brian Coss ,  Kanghoon Jeon

IPC: H01L29/66

CPC classification number: H01L29/66477 ,  H01L29/7391 ,  H01L29/78

Abstract: Horizontal and vertical tunneling field-effect transistors (TFETs) having an abrupt junction between source and drain regions increases probability of direct tunneling of carriers (e.g., electrons and holes). The increased probability allows a higher achievable on current in TFETs having the abrupt junction. The abrupt junction may be formed by placement of a dielectric layer or a dielectric layer and a semiconductor layer in a current path between the source and drain regions. The dielectric layer may be a low permittivity oxide such as silicon oxide, lanthanum oxide, zirconium oxide, or aluminum oxide.

Abstract translation: 在源极和漏极区之间具有突变结的水平和垂直隧道场效应晶体管（TFET）增加了载流子（例如，电子和空穴）的直接隧穿的概率。 增加的概率允许在具有突变结的TFET中更高的电流可实现。 可以通过在源极和漏极区域之间的电流路径中放置介电层或电介质层和半导体层来形成突变结。 电介质层可以是低介电常数氧化物，例如氧化硅，氧化镧，氧化锆或氧化铝。

公开(公告)号：US09029218B2

公开(公告)日：2015-05-12

申请号：US13856649

申请日：2013-04-04

Applicant: Sematech, Inc.

Inventor： Wei-Yip Loh ,  Brian Coss ,  Kanghoon Jeon

IPC: H01L21/336 ,  H01L29/66 ,  H01L29/78

CPC classification number: H01L29/66477 ,  H01L29/7391 ,  H01L29/78

Abstract: Horizontal and vertical tunneling field-effect transistors (TFETs) having an abrupt junction between source and drain regions increases probability of direct tunneling of carriers (e.g., electrons and holes). The increased probability allows a higher achievable on current in TFETs having the abrupt junction. The abrupt junction may be formed by placement of a dielectric layer or a dielectric layer and a semiconductor layer in a current path between the source and drain regions. The dielectric layer may be a low permittivity oxide such as silicon oxide, lanthanum oxide, zirconium oxide, or aluminum oxide.

Abstract translation: 在源极和漏极区之间具有突变结的水平和垂直隧道场效应晶体管（TFET）增加了载流子（例如，电子和空穴）的直接隧穿的概率。 增加的概率允许在具有突变结的TFET中更高的电流可实现。 可以通过在源极和漏极区域之间的电流路径中放置介电层或电介质层和半导体层来形成突变结。 电介质层可以是低介电常数氧化物，例如氧化硅，氧化镧，氧化锆或氧化铝。