公开(公告)号：US20140183597A1

公开(公告)日：2014-07-03

申请号：US13729592

申请日：2012-12-28

Applicant: SEMATECH, INC.

Inventor： Rinus Tek Po LEE ,  Tae Woo KIM ,  Man Hoi WONG ,  Richard HILL

IPC: H01L29/205

CPC classification number: H01L29/205 ,  H01L21/28575 ,  H01L29/452 ,  H01L29/4966 ,  H01L29/513 ,  H01L29/517 ,  H01L29/66522

Abstract: Semiconductor structures having a first layer including an n-type III-V semiconductor material and a second layer including an M(InP)(InGaAs) alloy, wherein M is selected from Ni, Pt, Pd, Co, Ti, Zr, Y, Mo, Ru, Ir, Sb, In, Dy, Tb, Er, Yb, and Te, and combinations thereof, are disclosed. The semiconductor structures have a substantially planar interface between the first and second layers. Methods of fabricating semiconductor structures, and methods of reducing interface roughness and/or sheet resistance of a contact are also disclosed.

Abstract translation: 具有包括n型III-V半导体材料的第一层和包括M（InP）（InGaAs）合金）的第二层的半导体结构，其中M选自Ni，Pt，Pd，Co，Ti，Zr，Y， Mo，Ru，Ir，Sb，In，Dy，Tb，Er，Yb和Te及其组合。 半导体结构在第一和第二层之间具有基本平坦的界面。 还公开了制造半导体结构的方法，以及降低接触面的界面粗糙度和/或薄层电阻的方法。