MERGED P-INTRINSIC-N (PIN) SCHOTTKY DIODE
    4.
    发明申请

    公开(公告)号:US20190267496A1

    公开(公告)日:2019-08-29

    申请号:US16406228

    申请日:2019-05-08

    Abstract: In a general aspect, a method can include forming a first pillar of a first conductivity type and a second pillar of a second conductivity type, alternately disposed with the first pillar. The second pillar can be in direct contact with the first pillar. The method can also include forming an implant of the second conductivity type in an upper portion of the second pillar. The implant can have a doping concentration that is higher than a doping concentration of a lower portion of the second pillar. The method can further include forming a Schottky metal layer having a first portion directly disposed on an upper surface of the first pillar and a second portion directly disposed on the implant along an upper surface of the second pillar. The first portion of the Schottky metal layer can be wider than the second portion of the Schottky metal layer.

    SPLIT TRENCH GATE SUPER JUNCTION POWER DEVICE

    公开(公告)号:US20210273091A1

    公开(公告)日:2021-09-02

    申请号:US16802718

    申请日:2020-02-27

    Inventor: Wonhwa LEE

    Abstract: A power semiconductor device includes a semiconductor layer having a first conductivity type. A pillar is provided in the semiconductor layer and has a second conductivity type that is different than the first conductivity type. A first trench gate is provided in the pillar proximate to a first vertical edge of the pillar. A second trench gate is provided in the pillar proximate to a second vertical edge of the pillar, the second vertical edge being on an opposing side of the pillar of the first vertical edge. A first electrode is provided over a first side of the semiconductor layer. A second electrode is provided over a second side of the semiconductor layer.

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